Re: FAQ #6 and #7 revised...

        Reply to: RE>FAQ #6 and #7 revised....

I still have a problem with understanding why ibis requires -Vdd to 2*Vdd
sweeps and how to generate data for ibis (FAQ #7, I am a good test case since
I started reading IBIS stuff a couple of days ago).

For Vout=-5V (or worse case -5.5V) it basically means very heavy forward
biasing of n+/p diode (in a standard output inverter configuration), which
might lead to diode destruction. Also Vout=+10V (or even +11V) could lead to
latchup or oxide breakdown. I believe this applies to most CMOS buffers
manufactured in submicron processes.
If I reduce these voltage limits then I can extrapolate to -Vdd and to 2*Vdd.
The problem is that I get very different answers depending what voltage I
chose (6,7 or 8V for example) as the last point measured and used for further
extrapolation. Extrapolation seems to imply that I-V characteristics is
linear, in fact it is not (avalanche multiplication effect for positive
voltages and forward diode conduction for negative voltages).

The bottom line is that depending how I do measurements or perform simulation
I will get different results at -Vdd/2*Vdd limits (as much as by a factor of
2).

Hoping to get some clarification on this...
Kris Iniewski
PMC-Sierra Inc.

--------------------------------------
Date: 8/21/95 4:01 PM
To: iniewski
From: Syed Huq
IBISfans,

As mentioned in the last IBIS Minutes (Aug11th'95), the last two
FAQ that need to be re-worded were #6 and #7.

I am attaching the revised answers based on some inputs I received.

Pls post your comment/changes/suggestions on the reflector and we
shall vote on this on the Aug25th meeting.

Regards,
Syed.
National Semiconductor.

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6.0 Can IBIS model SSO(Simultaneous Switching Output) ?

IBIS as a model, has all the parameters required to model an SSO event. These
are mainly the package inductance parameters and other associated parasitics.
IBIS specifies R, L and C in matrix format and the use of a matrix for the
inductance accounts for the "loop"inductance i.e. the mutuals between the
pins. Specifying the mutual inductance is necessary to account for SSO event
simulation. Modeling an SSO event is more of a simulator issue than IBIS.

7.0 Why do we need to sweep -Vcc to 2Vcc ?

Simulation accuracy is greatly enhanced by the "beyond-the-rail" data.
Overshoot and undershoot generally fall within this range, and the range
encompasses the forward-biased regions of protection diodes often used on
buffers. Also, reflections caused by improper terminations can produce
voltages at the driver/receiver terminals from -Vcc to 2Vcc. The drivers
and receivers, therefore, need to be modeled over this entire range.

Since measurement of diodes over the entire range is often not possible,
measurement over a reasonable range and extrapolation of data to the
end-point values is permitted to produce IBIS models.

Most non-SPICE based simulators will do their own extrapolation to get to
the end point. Most Spice simulators truncate data to the table
end-points.

The -Vcc to 2Vcc range ensures consistent performance for both types of
simulators.
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Date: Mon, 21 Aug 95 15:27:09 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9508212227.AA27399@rockie.nsc.com>
To: ibis@vhdl.org
Subject: FAQ #6 and #7 revised....
Received on Mon Aug 21 16:27:00 1995