IBIS Open Forum Meeting Minutes 2/6/95

Text item: Text_1

Date: Feb. 21, 1995

From: Will Hobbs (503) 696-4369, fax (503) 696-4210
         Will_Hobbs@ccm.jf.intel.com
         XTG Modeling Manager, Intel Corp., Chairperson, IBIS Open Forum
         Intel Corporation
         5200 NE Elam Young Pkwy, Hillsboro, OR 97124 USA
         and
         Derrick Duehren (503) 696-4299, fax (503) 696-4904
         Derrick_Duehren@ccm.jf.intel.com
         Intel Program Manager

Subject: Minutes from IBIS Open Forum Meeting 2/6/95

To:
Apple Computer Duane Talsahashi*
ARPA Randy Harr
AT&T Global Info Solutions Dave Moxley
Anacad Steffen Rochel
Ansoft Henri Maramis
Atmel Corporation Dan Terry
Cadence Design Sandeep Khanna, C. Kumar*
Cadlab Ralf Bruning
Contec Dileep Divkar*
Digital Equipment Corp. Barry Katz
EIA Patty Rusher
High Design Technology Michael Smith, Dr. Ing. Cosso
HP Palo Alto Tom Langdorf
HP EESof Karl Kachigan*, Henry Wu*
HyperLynx Kellee Crisafulli*
IBM Jay Diepenbrock, Joseph Flanigan
IBM-Motorola alliance Lynn Warriner, John Burnett
INCASES Werner Rissiek, Olaf Rethmeier
Integrated Silicon Systems Eric Bracken
Intel Corporation Stephen Peters*, Don Telian, Will Hobbs*
                              Arpad Muranyi*, Derrick Duehren*
Interconnectix, Inc. Bob Ross*
Intergraph Ian Dodd*, David Wiens, Walter Katz
IntuSoft Charles Hymowitz
Mentor Graphics Ravender Goyal, Greg Doyle
Meta-Software Mei Wong, You-Pang Wei*, John Sliney
MicroSim Arthur Wong
National Semiconductor Syed Huq*, Raj Raghuraum(?)*, Atul Agarwal*
NEC Hiroshi Matsumoto
North Carolina State U. Steve Lipa, Michael Steer
OptEM Engineering, Inc. Benny Leveille, Ken Ehn
Pacific Numerix Paul K. U. Wang*
PC Ware Paul Munsey, Ron Neville
Quad Design Jon Powell*
Quantic Labs Mike Ventham*
Racal-Redac John Berrie
Symmetry Martin Walker
Synopsys, Logic Modeling G. Bill Lattin
Texas Instruments Bob Ward*
Thomson-CSF/SCTF Jean Lebrun
UniCAD Canada Ltd. Stephen Lum*
Zeelan Technology George Opsahl, Hiro Moriyasu*

CC:
Intel Corporation Randy Wilhelm, Jerry Budelman,
                              Intel IBIS team

In the list above, attendees at the meeting are indicated by *.

Upcoming Meetings: The room and bridge numbers for future IBIS teleconferences
are listed below:
     Date Bridge Number Reservation #
     2/24/95 (916) 356-9999 457668

All meetings are 8:00 AM to 10:00 AM Pacific Time (16:00 to 18:00 UTC). We try
to have agendas out 7 days before each open forum and meeting minutes out
within 7 days after. When you call into the meeting, ask for the IBIS Open
Forum hosted by Will Hobbs and give the reservation number.

NOTE: "AR" = Action Required.

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Check-in, Intros, Announcements
All 22 participants introduced themselves and Ian Dodd "won the world"
sweepstakes (an Intel travel alarm clock).

New Agenda Items:
Release of Golden Parser 2.1 object code (Syed)
New Keyword (Bob Ward)

EIA discussion

Spice to IBIS: Anyone can create one.

We discussed three options for dues.
1. $500 dues will be collected annually in January. Companies that have
already paid $500 for the 2.1 Golden Parser will have their 1995 waived.

2. $500 dues will be collected annually in January. Companies that have
already paid $500 for the 2.1 Golden Parser will have their 1995 dues reduced
to $250 if they paid in 1994. If paid in 1995, the fee will be waived.

3. $500 dues will be collected annually in January. Golden Parser source will
be $500. If a company is a membership, they can license the source code for
$250, for a total of $750. Companies that have already paid $500 for the 2.1
Golden Parser will only pay $250 incremental for membership and the Golden
Parser.

The forum approved #3 unanimously.

AR Will/Derrick -- Resolve alias-list problems. [Update, Derrick now owns the
lists and receives all ibis-request mail, although is having technical
difficulties telnetting to make the changes.]

We agreed to have the funds in our IBIS account at Conference Management
Systems roll over into EIA.

AR Patti -- Send out letter to each company to confirm intent to join.

Kellee pointed out that the executable version of the parser needs to be
explicitly reserved for public-domain distribution.

The license fee for the Golden Parser will be one-time, with rights to use
forever.

Future Direction Discussion (Will Hobbs)
Will briefly summarized IBIS's history from its beginning in 1993. And
introduced potential future directions/projects for the forum:

o Fund computer programs for making it easier to create IBIS models. For
  example, a project to create a Windows/UNIX editor with the Golden Parser
  built in (PERL/Auk scripts or Excel spreadsheet macros).

o Actively encourage creation of model libraries.

o Make clear the stability of V1.1 and V2.1, obsolescence immunity.

o EDA vendors implement V2.1.

o EIA affiliation (in process).

o Formation of a separate IBIS users group for model developers (conference
  and technical forum). Possibly using a WWW home page, internet newsgroup,
  SI list, mail list (newsletter).

o Publish articles, books, press releases.

o Update the cookbook to V2.1.

o Publicize the reflector, vhdl.org.

o Add more models to the vhdl.org library. publicize them.

o DAC IBIS booth. "IBIS supporter" stand-up placards for DAC. As new interim
  vice-chair, Jon Powell will coordinate the creation and distribution of the
  placards.

o Create an IBIS modeling company. A decryption Application Programmable
  Interface may be needed to help enable charging fees for IBIS models.

o V3.0 Suggestions.
  - Improved package elements
  - Improve diode modeling: transit time, charge storage
  - Refine SSO modeling
  - Support noise injection on Vcc
  - Support feedback
  - Curve scaling (T,V) from typical to min, max
  - Model additional devices (transistors, analog I/O, ???)
  - EMI, microwave
  - Power modeling
  - Support for static timing

o Potential new uses/arenas for IBIS
  - Integrate with VHDL and Verilog for mixed simulation, timing
  - Electronic data book element
  - Bi-directional medium for information exchange between component
    architects, system designers, and I/O buffer designers

o Need to grow the IBIS tool kit
  - Data-extraction methodologies (improved techniques, expanded cookbook,
    auto-extraction tools, auto-validation tools [silicon and simulation])
  - Improve silicon testing and offer guaranteed models
  - Improve Golden Waveform support by EDA and model vendors
  - Create a compliance test suite

Diode Storage Effects (Tim Schryer, Intel)
Tim was unable to participate.

Diode Storage Effects (Jon Powell, Quad)
Jon Powell discussed diode turn-on time, charge storage.

He has been exploring how to extract information that can be represented in
IBIS format. E.g., a voltage/capacitance array. Transit time approach is well
stated and is in Spice already, but it is tough to measure and formulate, so it
is less desirable for IBIS. The IBIS spec assumes that diodes turn on/off
instantaneously. There is a time delay due to the stored charge in the diode.
Jon invited any interested parties to devise a means of adding diode storage
effects to the IBIS standard.

Arpad discussed the difficulty of measuring capacitance with readily available
equipment. He noticed that when a sweep goes from low-to-high and high-to-low,
he gets a different result. He found he could reverse engineer the capacitance
through an averaging process.

Hiro Moriyasu shared his experience with actual measurement experience. As you
switch from - to + through a resistor, stored charge causes a delay, a step in
the voltage as measured at the diode, for a time related to the size of
capacitance. Td/tau = ln(1 + (If/Ir)), where If = forward bias current and Ir
= reverse bias current. tau is a range of 20 -100 nS over reasonable operating
ranges, and this technique predicts well within 10%. This was described as we
went from forward to reverse biased. You don't see this effect when going from
reversed to forward biased. Zeelan measured in the latter case and does not
see the delay.

Arpad described experience with a 74F part that has a speed-up diode on the
input. He found that he could simulate it with a capacitor that is switched in
for one transition (forward to reverse bias transition) and out for the other.

We'd like a behavioral diode description. We'd like a way to take spice and
measured data and convert it into this behavioral way.

A voltage-dependent resister may be a valid method.

AR Arpad, Hiro, and Jon -- Post a description of your approaches to diode
storage effects to the reflector. We will attempt to converge on a behavioral
representation that captures the essential elements or the best of the three.

Handling Multiple Personality Drivers Discussion (Bob Ward, TI)
Bob Ward described a chip that has a "personality pin" that allows a driver to
be switched from TTL to CMOS to GTL, and some customer wants to do this
dynamically! At 1.5 V on the personality pin, one type of output is enabled,
another for 1.5V - 2.5V, and the third for >2.5V. Ian Dodd suggested three
models in parallel with separate enables. Hiro suggested driving the enable
pin with analog comparators. Jon and Kellee discussed ways of specifying
multiple models for the same pin and selecting between them. For example,
"Pin, model, model, model".

Jon suggested adding hints in cookbook on how to handle multiple driver
personalities per pin.

Hiro mentioned that VHDL-A handles this type of case (1076.1)

Issues Regarding Min and Max Model Data (Bob Ross, Interconnectix)
Bob Ross discussed Min and Max data and characterization.

2 Paradigms:
1) min corresponds to min data, max to max data.
2) min corresponds to the min process corner, max to max corner (e.g., min
   capacitance => max speed). This relates to Bird 25.

For temperature in V2.1, temperature is specifically called out for CMOS min to
correspond to highest temperature value.

Hiro pointed out we have 3 axes to deal with, given environment and process
(voltage, temperature, process).

The main thrust of the presentation was clarity of the spec. Another way of
handling it is with new keywords that call out what columns to use for fast and
slow behavior. Absolute value of voltage is not clearly spelled out, either:
for ECL, increasing the absolute value for the power supply corresponds to
making it go farther below zero.

Arpad suggested a counter-example of max capacitance == slow; big transistor =
fast; and = big c_comp.

We may also want to call out/highlight the Data Derivation section at the front
of the spec.

We agreed that this issue is one of clarifying/interpreting the spec. Bob will
update BIRD 25 to reflect the issues discussed.

On another subject, Bob said that when min or max columns are not present and a
min or max simulation is being done, everyone generally defaults to typ. For
waverform tables, however, this is not a good assumption. What do you do when
all three columns are not present? E.g., if running min simulation and only
typ and max waveform tables are available, Bob suggests reverting to dv/dt_r
min instead of typical waveform table. Jon P. disagrees, Will suggested it is
the model provider's job to make sure this doesn't get done.

Bob also suggested aligning waveform tables to start at 0 nS or to shift them
to align all at same point (5 nS, e.g.). Waveform priority: use first one.
Waveform test load priority: favor resistive loads. Few or many points? Vary
v_fixture of r_fixture? CMOS, TTL, ECL strategies?

AR Intel -- Determine how the Intel-posted models handle these issues and
report to Bob Ross.

AR Bob Ross -- Update BIRD 25. [Done, below]

   Based on 2/6/95 discussions, BIRD25.1 is issued. It contains an initial
   statement to point to the Notes on Data Extraction per Karl Kachigan's
   suggestion. It also changes the default of C_comp to be consistent with
   existing practice when min and max values are given independent of process
   information. This is the major change from BIRD25. There are also some
   minor text corrections.

Gate Modulation and Replacing Min. and Max. Tables with Scaling (Arpad Muranyi,
Intel)
Arpad presented a proposal for replacing the Min. and Max. tables with x-scale,
x-shift, y-scale, y-shift scaling parameters for Vcc and Temp. Arpad proposes
that this mechanism could provide more detailed and efficient ways to describe
the effects of Vcc and temperature variations.

Arpad discussed gate modulation: ground bounce causes pre-driver to shift
relative to output driver, causing a shift in output V/I. Does IBIS contain
enough data to model this effect?

In regard to scaling, Arpad showed that under normal conditions, V/I tables can
be scaled by some K factor for voltage and temperature.

Iout = Kvcc*Vgs*IV@5V, where Kvcc is the scaling factor and Vgs = instantaneous
die Vcc. Perhaps we could have a separate scaling factor for temperature,
voltage and process. Complications arise from the fact that some parameters
scale, while others shift (n-channel pullups versus clamping diodes, e.g.; or,
VT curves may scale on time axis but not on voltage axis). Problem could be
solved with separate x and y shift and scaling values for temperature and
voltage.

What is missing from this is the charge storage in the buffers that resist
change to gate modulation effects, and Vcc ringing. We still don't know the
skew between buffers turning on.

Inter-simulation Correlation Discussion (Will Hobbs)
Not discussed due to lack of time.

Alternative Packaging Representations Discussion (Stephen Peters)
Stephen presented an expanded proposal for representing packages. Jon Powell
expressed concern over using this proposal with Multi-chip module parts.

Wrap-up, Next Meeting Plans
Our next meeting is a "normal" teleconference 2/24/95.

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                                      NOTES
If you know of someone new who wants to join the e-mail reflector
(ibis@vhdl.org), send e-mail to ibis-request@vhdl.org.

Check the pub/ibis directory on vhdl.org for more information on previous
discussions and results. You can get on via ftp anonymous, "guest" login from
telnet or dial-in (415-335-0110), or send an email request to the automatic
archive server, archive@vhdl.org.
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Received on Tue Feb 21 11:48:40 1995