I am resending this egg because it didn't seem to go out the first
time. If you already received it, ignore this copy.
Proposed IBIS physical package Format (.IBP)
Version 0.15
10-29-95
Versions:
0.1 7-30-95
0.15 10-29-95
Introduction
This is a first draft of a proposal to allow physical package models of
IC's, MCM's and circuit boards such as SIMM memory modules to be described
in combination with the existing IBIS model specification.
The .IBP file is a higher level of abstraction above the .IBS file. For
example if this format is used to represent a SIMM module then the the .IBS
components contained within it can be modified to support memory devices
from Toshibia, NEC, TI etc by simply changing the references to the .IBIS
files. Like wise if the .IBP file is used to represent an MCM model the
.IBS file would represent the bare die. If the .IBP file is used to
represent the package of an IC model than the .IBS file would again be the
bare die information only.
This format allows layered metal conductors and dielectric layers to be
specified as well as
interconnections between layers.
The advantages of this format over other existing standards are:
- Simple compared to most existing PCB standards.
- Allows layers to be specified
- Allows component values to be specified
- Allows IC types to be specified in IBIS format
Translators:
To create translators to this format RSI could be contracted to create a
writer and
make available translators from all of the 30+ PCB file
formats they support into this
format. Most CAE companies are probably already familar with RSI.
If you have comments please contact Kellee Crisafulli:
Internet: kellee@hyperlynx.com
voice 206-869-2320
fax 206-881-1008
Overview of a .IBP File's Format:
{VERSION=number [comment]}
{SUBSTRATE_OUTLINE
(outline information) [comment]
...
(outline information)
}
{STACKUP
(layer information) [comment]
...
(layer information)
}
{DEVICES
(device information) [comment]
(device information)
...
(device information)
}
{PADSTACK=name
(pad information) [comment]
(pad information)
...
(pad information)
}
{PADSTACK=name
(pad information)
(pad information)
...
(pad information)
}
...more padstacks...
{NET=name
(segment/arc/via/pin information) [comment]
(segment/arc/via/pin information)
...
(segment/arc/via/pin information)
}
{NET=name
(segment/arc/via/pin information)
(segment/arc/via/pin information)
...
(segment/arc/via/pin information)
} ...more nets...
{NET=name
(segment/arc/via/pin information)
(segment/arc/via/pin information)
...
(segment/arc/via/pin information)
}
{END}
Notes on Detailed Syntax of .IBP File
This file follows the specifications created for the IBIS file in that:
- It is an ASCII human readable specification
- It uses the same units and scaling notation as the IBIS specification
- It uses a similar format
Differences with the IBIS specification are:
- Line length is allowed to be 180 characters
Italicized fields are to be filled in with appropriate values.
Square brackets [ ] denote optional parameters.
Subrecord fields [lines beginning with ')'] can come in any order, but the
specified order is recommended for readability.
All subrecords must be on a single line. This is true in spite of the fact
that, for readability, some subrecords in this document are shown on
multiple lines.
Curly braces { } can be separated from keywords and record ends by white
space; the right brace can be on the same line as the last subrecord or on
the next line.
Parentheses ( ) can be separated from keywords and subrecord ends by white
space; must be on the same line as the subrecord.
Comments must be separated by at least one white space from the preceding text.
Lines can be terminated by CR, LF, CR-LF, or LF-CR.
White space is defined as space, horizontal tab, vertical tab, linefeed,
form feed, or carriage return.
White space is NOT allowed after or in a name field.
Keyword VERSION
Format:
{VERSION=number [comment]}
o VERSION specifies the version of the file format
o number specifies the .IBP-file version number
o required record; must be the first non-blank line in file
o only one VERSION record allowed per file
Example Records for VERSION:
example 1:
{VERSION=1.0}
example 2:
{VERSION=1.0 written from ABC's PCB layout package}
Keyword SUBSTRATE_OUTLINE
Format:
{SUBSTRATE_OUTLINE [comment]
(PERIMETER_SEGMENT X1=position Y1=position X2=position Y2=position)
[comment]
...more perimeter segments...
(PERIMETER_ARC X1=position Y1=position X2=position Y2=position
XC=position YC=position R=radius) [comment]
...more perimeter arcs...
}
o SUBSTRATE_OUTLINE identifies the board or substrate edge. This is useful
for display
purposes, and to calculate impedances of conductors near the edge the board.
o optional record; if missing, the SUBSTRATE_OUTLINE outline is assumed to
be rectangular, and is determined as the position of the most-extreme
component pins or traces present.
o the SUBSTRATE_OUTLINE record can also be used to specify holes and other
cut-outs in the interior of the package substrate. For example mounting
holes, or alignment holes like those used for SIMM modules
o PERIMETER_SEGMENT record reports information for straight segments of the
board's perimeter
o units throughout subrecord are as specified in the UNITS record
o X1, Y1, X2, or Y2 position is the x or y position of end 1 or end 2 of
the segment
o PERIMETER_ARC record reports information for arcs on the board's perimeter
o Arc's are drawn clockwise from X1,Y1 to X2,Y2
o units throughout subrecord are as specified in the UNITS record
o X1, Y1, X2, or Y2 position is the x or y position of end 1 or end 2 of
the arc
o XC or YC position is the position of the center of the arc
o R radius is the radius of the arc
o each PERIMETER_SEGMENT record must be on a single line
o only one SUBSTRATE record allowed per file
Example Records for SUBSTRATE_OUTLINE:
example 1:
{SUBSTRATE_OUTLINE rectangular board with edge connector
(PERIMETER_SEGMENT X1=0.0 Y1=0.0 X2=12.0 Y2=0.0)
(PERIMETER_SEGMENT X1=12.0 Y1=0.0 X2=12.0 Y2=-5.0)
(PERIMETER_SEGMENT X1=12.0 Y1=-5.0 X2=3.0 Y2=-5.0)
(PERIMETER_SEGMENT X1=3.0 Y1=-5.0 X2=3.0 Y2=-5.5) connector segment
(PERIMETER_SEGMENT X1=3.0 Y1=-5.5 X2=0.5 Y2=-5.5) connector segment
(PERIMETER_SEGMENT X1=0.5 Y1=-5.5 X2=0.5 Y2=-5.0) connector segment
(PERIMETER_SEGMENT X1=0.5 Y1=-5.0 X2=0.0 Y2=-5.0)
(PERIMETER_SEGMENT X1=0.0 Y1=-5.0 X2=0.0 Y2=0.0)
}
Keyword STACKUP
Format:
{STACKUP [comment]
(SIGNAL T=thickness [P=plating_thickness] [C=constant] L=layer_name
[M=material_name]) [comment]
...more signal layers...
(DIELECTRIC T=thickness [C=constant] [L=layer_name] [M=material_name])
[comment]
...more dielectric layers...
(PLANE T=thickness [C=constant] [L=layer_name] [M=material_name]) [comment]
...more plane layers...
}
o STACKUP identifies the stackup-specification record
o optional record; if missing, stackup is built as layer names encountered
in NET and PADSTACK subrecords; first layer encountered becomes top layer,
next becomes second-from-top, etc.
o subrecords can be mixed in any order that correctly describes the
PACKAGE's top-to-bottom construction; the first SIGNAL or PLANE layer will
be numbered 1 (top), the next 2 (second from the top), and so forth
o SIGNAL record reports information for signal layers
o units throughout subrecord are as specified in the UNITS record
o thickness specifies how thick the metal is
o optional plating_thickness specifies how thick the metal plating is; if
missing, assumed to be 0.0
o optional constant specifies resistivity; if missing, assumed to be
1.724e-8 (copper)
o layer_name specifies a name for the layer; maximum of 20 characters;
layers reported in NET subrecords are matched to these names
o optional material_name specifies a name for the trace material; maximum
of 20 characters
o DIELECTRIC record reports information for dielectric layers
o units throughout subrecord are as specified in the UNITS record
o thickness specifies how thick the dielectric is
o optional constant specifies the dielectric constant; if missing, assumed
to be 4.8 (FR-4)
o optional layer_name specifies a name for the layer; maximum of 20 characters
o optional material_name specifies a name for the dielectric material;
maximum of 20 characters
o PLANE record reports information for power-plane layers
o units throughout subrecord are as specified in the UNITS record
o thickness specifies how thick the metal is
o optional constant specifies resistivity; if missing, assumed to be
1.724e-8 (copper)
o optional layer_name specifies a name for the layer; maximum of 20
characters; layers reported in NET subrecords are matched to these names
o optional material_name specifies a name for the plane material; maximum
of 20 characters
o each SIGNAL, PLANE, or DIELECTRIC record must be on a single line
o only one STACKUP record allowed per file
Example Records for STACKUP:
example 1:
{STACKUP 4-layer PACKAGE; units for this example are English, weight
(SIGNAL T=0.0014 P=0.0014 L=TOP) 1-oz base and plating; resistivity = 0.0
(DIELECTRIC T=0.02 C=4.8)
(PLANE T=0.0014 L=2) by default plating=0.0 and resistivity = copper
(DIELECTRIC T=0.01 C=4.8)
(PLANE T=0.0014 L=3) by default plating=0.0 and resistivity = copper
(DIELECTRIC T=0.02 C=4.8)
(SIGNAL T=0.0014 P=0.0014 L=BOTTOM)
}
example 2:
{STACKUP same example, except this one includes resistivities and some
layer and material names
(SIGNAL T=14e-3 P=14e-3 C=0.017u L=TOP) 1-oz base and plating;
resistivity = copper's
(DIELECTRIC T=0.02 C=4.8 M=FR4)
(PLANE T=14e-3 C=0.017u L=Vcc)
(DIELECTRIC T=0.01 C=4.8 M=FR4)
(PLANE T=14e-3 C=0.017u L=GND)
(DIELECTRIC T=0.02 C=4.8 M=FR4)
(SIGNAL T=14e-3 P=14e-3 C=0.017u L=BOTTOM)
}
Keyword DEVICES
Format:
{DEVICES [comment]
(IC REF=reference_designator NAME=name.IBS L=layer_name [comment]
...more ICs...
(R REF=reference_designator VAL=value L=layer_name) [comment]
...more resistors...
(C REF=reference_designator VAL=value L=layer_name) [comment]
...more capacitors...
(J REF=reference_designator NAME=name L=layer_name) [comment]
...more connectors...
}
o DEVICES identifies the device-specification record
o required record
o any non-zero number of these subrecords may follow: IC, R, C, J
IC subrecord
o IC record reports information for ICs (drivers and receivers)
o reference_designator specifies the IC's reference designator
o name specifies the IBIS model file name.
Only file name and extension are provide.
File path information must not be included.
o layer_name is the name of the layer which the device is on
R subrecord
o R record reports information for resistors
o reference_designator specifies the resistor's reference designator
o value specifies the resistor's value, in ohms
o layer_name is the name of the layer which the device is on
C subrecord
o C record reports information for capacitors
o reference_designator specifies the capacitor's reference designator
o value specifies the capacitor's value, in Farads
o layer_name is the name of the layer which the device is on
J subrecord
o J record reports information for connectors
o reference_designator specifies the connector's reference designator
o value specifies the connector's name (e.g. ABC 11345AG68) vendor specific
name
o layer_name is the name of the layer which the device is on
Note: The special layer name EDGE is used to specify that the connector is
an edge connector or wraps around both sides of the board or substrate.
o Each device-type record must be on a single line.
o Only one DEVICES record is allowed per file.
o Future versions may choose to add more passive devices. For the initial
release, only capacitors and resistors may be specified. This should cover
most small modules and MCM's. The number of component types that could be
added in the future could include dozens of component types. To keep the
specification simple for the first release other componet types are not
allowed.
Example Records for DEVICES:
example 1:
{DEVICES
(IC REF=U13 NAME=XC_4010.IBS L=TOP) Xilinx LCA; on top layer
(IC REF=U20 NAME=82374.IBS L=8) Intel chip on layer 8 (back side of
substrat)
(R REF=R15 VAL=1K L=TOP) resistance = 1000 ohms
(C REF=C1 VAL=22p L=8) capacitance = 22 pF
(R REF=R15 VAL=5n) inductance = 0.005 uH
(J REF=J2 NAME=Amp_HDI100 L=TOP) Amp HDI 100 pin connector
}
Keyword PADSTACK
Format:
{PADSTACK=padstack_name, [drill_size]
(layer_name, pad_shape, pad_sx, pad_sy, pad_angle, [thermal_clear_shape],
[thermal_clear_sx], [thermal_clear_sy], [thermal_clear_angle], [pad_type])
[comment]
...more padstack elements...
(layer_name, pad_shape, pad_sx, pad_sy, pad_angle, [thermal_clear_shape],
[thermal_clear_sx], [thermal_clear_sy], [thermal_clear_angle], [pad_type])
[comment]
}
o PADSTACK identifies the padstack-specification record
o at least one padstack-element subrecord must follow
o a comment is not allowed on the PADSTACK line, owing to the
fixed-position nature of this record; comments are allowed on ensuing lines
with padstack-element subrecords
o padstack_name is a unique a name for this padstack; maximum of 32
characters and cannot contain white space
o optional drill_size is the diameter of the padstack's drill hole, if any;
if there is no drill hole, may omit this parameter; drill_size is the
diameter of the drill hole before plating (hole plating is specified by the
STACKUP record and is the same as the outside-layer plating thickness)
o NOTE: The format of the PADSTACK record differs somewhat from the other
records in the .IBP file, in that PADSTACK is fixed-position rather than
keyword-based. This means that all parameters must come in the specified
order (optional parameters are always at the end of a line). This change (to
a fixed-position format) has been introduced to shorten the length of the
.IBP file.
Padstack-element subrecord
o padstack-element record reports information for individual pads in a padstack
o units throughout subrecord are as specified in the UNITS record
o layer_name is name of the layer which the pad is on; valid values are:
user_name
MDEF
ADEF
where user_name is any user-created name that does not violate .IBP-file syntax
MDEF is a special, reserved layer name indicating that all layers have this
default metal pad unless otherwise specified with an explicit
padstack-element
subrecord
ADEF is a special, reserved layer name indicating that all plane layers
defined in
the STACKUP record will have this default anti-pad unless otherwise specified
with an explicit padstack-element subrecord (an 'anti-pad' defines the
size and
shape of a non-conducting hole in a plane layer through which a via passes)
o if layer_name does not match a name already in the PACKAGE's stackup, a
new layer with name layer_name will be created
o pad_shape is the shape of the pad; valid values are: 0, 1, 2
where '0' means oval or round (pad_sx = pad_sy if round)
'1' means rectangular or square (pad_sx = pad_sy if square)
'2' means oblong (oblong shape is a rectangle with rounded corners)
o pad_sx or pad_sy is the x or y dimension of the pad
o pad_angle is the counter-clockwise rotation angle of the pad in degrees;
rotation angle can range from 0.0 to +/-359.999; valid angular resolution is
0.001 degree; 0 (without a decimal point) is the recommended way of
specifying 'no rotation'
o thermal_clear_shape (required only if pad_type is T, thermal relief) is
the shape of the clear area around a thermal-relief pad; valid values are:
0, 1 , 2
where '0' means oval or round (thermal_clear_sx = thermal_clear_sy if round)
'1' means rectangular or square (thermal_clear_sx = thermal_clear_sy if
square)
'2' means oblong (oblong shape is a rectangle with rounded corners)
o thermal_clear_sx or thermal_clear_sy (required only if pad_type is T,
thermal relief) is the x or y dimension of the clear area around a
thermal-relief pad
o thermal_clear_angle (required only if pad_type is T, thermal relief) is
the counter-clockwise rotation angle of the clear area around a
thermal-relief pad, in degrees; rotation angle can range from 0.0 to
+/-359.999; valid angular resolution is 0.001 degree; 0 (without a decimal
point) is the recommended way of specifying 'no rotation'
o if any one of thermal_clear_sx, thermal_clear_sy, or thermal_clear_angle
is specified, all three must be specified and the pad_type must be specified
as T
o optional pad_type specifies whether the pad is a normal metal pad, an
anti-pad, or a thermal relief; if missing and three x/y/angle parameters
specified, the pad is assumed to be a normal metal pad; if missing and six
x/y/angle parameters specified, the pad is assumed to be a thermal-relief
pad; valid values are:
M
A
T
where 'M' means normal metal pad (used for signal vias and component pads)
'A' means anti-pad (used to define non-conducting hole through a plane layer)
'T' means a thermal-relief pad (used to connect a pad to a plane layer)
o NOTE: Anti-pads are not required; a padstack not using anti-pads can
simply omit information about plane layers.
Example Records for PADSTACK:
example 1: rectangular surface-mount pad on the top layer; spaces after
commas are not required
{PADSTACK=SMT001
(TOP, 1, 0.04, 0.08, 0)
}
example 2: round surface-mount pad on bottom layer; PACKAGE has 16 layers
and layer names are numeric
{PADSTACK=PSTK-054
(16,0,0.04,0.04,0)
}
example 3: oblong surface-mount pad on bottom layer, at 45-degree angle
{PADSTACK=SMT003
(BOTTOM, 2, 0.04, 0.06, 45.0)
}
example 4: through-hole, 60-mil-diameter round pads on all layers with a
30-mil-diameter drill hole
{PADSTACK=STD1, 0.03
(MDEF, 0, 0.06, 0.06, 0)
}
example 5: through-hole, 60-mil-diameter round pads on all layers except
layer 1; layer 1 has a 60-mil-wide square pad; drill hole is 30 mils in diameter
{PADSTACK=STD1, 0.03
(1, 1, 0.06, 0.06, 0)
(MDEF, 0, 0.06, 0.06, 0)
}
example 6: through-hole padstack; 60-mil-wide square pad on layers 1 and 8;
60-mil-diameter round pads on layers 2 and 7; no pads on layers 3 and 6;
60-mil-diameter round thermal-relief pad with 100-mil-diameter round clear
area on layer 4;100-mil-diameter round anti-pad on layer 5
{PADSTACK=STD1, 0.03
(1, 1, 0.06, 0.06, 0)
(2, 0, 0.06, 0.06, 0, M) pad type 'M' not required
(4, 0, 0.06, 0.06, 0, 0, 0.10, 0.10, 0, T) thermal pad
(5, 0, 0.10, 0.10, 0, A) anti-pad
(7, 0, 0.06, 0.06, 0)
(8, 1, 0.06, 0.06, 0)
}
Keyword NET
Format:
{NET=name [comment]
(SEG X1=position Y1=position X2=position Y2=position W=width
L=layer_name)
[comment]
...more segments...
(ARC X1=position Y1=position X2=position Y2=position XC=position
YC=position R=radius
W=width L=layer_name) [comment]
...more arcs...
(VIA X=position Y=position [L1=layer_name] [L2=layer_name]
P=padstack_name) [comment]
...more vias...
(PIN X=position Y=position R=reference_designator.pin_name P=padstack_name
[F=function]) [comment]
...more pins...
}
o NET identifies a net-specification record
o name is the net's name
o any non-zero number of these subrecords may follow: SEG, ARC, VIA, and PIN
SEG subrecord
o SEG record reports information for straight metal trace segments
o units throughout subrecord are as specified in the UNITS record
o X1, Y1, X2, or Y2 position is the x or y position of end 1 or end 2 of
the segment
o width is the segment's width
o layer_name is name of the layer which the segment is on; if layer_name
does not match a name already in the PACKAGE's stackup, a new layer with
name layer_name will be created
Example Records:
example 1: a simple trace segment; 10 mils wide; on layer "top"
(SEG X1=1.0 Y1=0.5 X2=1.0 Y2=1.8 W=0.01 L=top)
example 2: a 45-degree trace segment; 15 mils wide; on layer 3; note lack of
case-sensitivity
(seg x1=1 y1=1 x2=2 y2=2 w=15e-3 l=3)
How to draws a segment:
ARC subrecord
o ARC record reports information for curved metal trace segments
o units throughout subrecord are as specified in the UNITS record
o X1, Y1, X2, or Y2 position is the x or y position of end 1 or end 2 of
the arc
o XC or YC position is the x or y position of the center of the arc
o R radius is the radius of the arc
o width is the arc's metal width
o layer_name is name of the layer which the arc is on; if layer_name does
not match a name already in the PACKAGE's stackup, a new layer with name
layer_name will be created
o The arc is drawn clockwise from X1,Y1 to X2,Y2
Example Records:
example 1: a curved trace segment; radius of a half inch; 10 mils wide; on
layer "top"
(ARC X1=1.0 Y1=1.0 X2=1.0 Y2=2.0 XC=1.0 YC=1.5 R=0.5 W=0.01 L=top)
VIA subrecord
o VIA record reports information for vias; use for vias where no component
pin is present; if there is a component pin, use a PIN record instead
o units throughout subrecord are as specified in the UNITS record
o X or Y position is the x or y position of the via
o optional L1 layer_name is the name of the layer the via starts on; if
missing, assumed to be the top layer; if layer_name does not match a name
already in the PACKAGE's stackup, a new layer with name layer_name will be
created
o optional L2 layer_name is the name of the layer the via ends on; if
missing, assumed to be the bottom layer; if layer_name does not match a name
already in the PACKAGE's stackup, a new layer with name layer_name will be
created
o padstack_name is the name of the padstack associated with the via; must
match the name of a padstack reported in a PADSTACK record
Example Records:
example 1: a via between layers TOP and BOT; pads defined in padstack STD1
(VIA X=2.35 Y=4.05 L1=TOP L2=BOT P=STD1)
example 2: same as example 1, except layers are missing, so assumed to be
top and bottom
(VIA X=2.35 Y=4.05 P=STD1)
example 3: a via connecting two trace segments on top layer and layer "foo"
(VIA X=5 Y=6.95 L2=foo P=STCK002)
PIN subrecord
o PIN record reports information for a component pin
o units throughout subrecord are as specified in the UNITS record
o X or Y position is the x or y position of the component pin
o reference_designator.pin_name is the reference designator and pin name of
the component pin
o padstack_name is the name of the padstack associated with the pin; must
match the name of a padstack reported in a PADSTACK record
Example Records:
example 1: pin 4 on U3, with surface-mount pad defined by padstack SMD1
(PIN X=7.55 Y=9.15 R=U3.4 P=SMD1)
example 2: pin 2 of resistor R2
(PIN X=0.05 Y=1 R=R2.2 P=FOO)
o as many of each net subrecord (SEG, ARC, VIA, and PIN) per NET record as
needed are allowed; subrecords can come in any order
o as many NET records per file as needed are allowed
Example Records for NET:
example 1: a complete trace, with 4 segments; 3 vias connecting the
segments; an IC pin at one end
{NET=clock
(VIA X=1.0 Y=1.0 L1=TOP L2=BOT P=PS002)
(SEG X1=1.0 Y1=1.0 X2=1.95 Y2=1.0 W=.01 L=TOP) segment 1
(VIA X=1.95 Y=1.0 L1=TOP L2=2 P=PS002) connecting via
(SEG X1=1.95 Y1=1.0 X2=1.95 Y2=1.2 W=.008 L=2) segment 2
(VIA X=1.95 Y=1.2 L1=2 L2=6 P=PS002) connecting via
(SEG X1=1.95 Y1=1.2 X2=2.65 Y2=1.2 W=.008 L=6) segment 3
(VIA X=2.65 Y=1.24 L1=TOP L2=BOT P=PS002) connecting via
(SEG X1=2.65 Y1=1.2 X2=4 Y2=2.2 W=.01 L=BOT) segment 4
(PIN X=4 Y=2.2 R=U17.4 P=PS005) surface-mount IC pin
}
Keyword END
Format:
{END}
o END identifies the end of the PCB-layout data
A Complete .IBP File with Two Nets:
{VERSION=1.10}
{SUBSTRATE_OUTLINE
(PERIMETER_SEGMENT X1=0.0cm Y1=0.0c X2=8.0c Y2=0.0c)
(PERIMETER_SEGMENT X1=8.0cm Y1=0.0c X2=8.0c Y2=8.0c)
(PERIMETER_SEGMENT X1=8.0c Y1=8.0c X2=0.0c Y2=8.0c)
(PERIMETER_SEGMENT X1=0.0c Y1=8.0c X2=0.0c Y2=0.0c)
}
{STACKUP
(SIGNAL T=35u P=35u L=TOP) 35 micro meters thick -> 1 oz copper
(DIELECTRIC T=254u) 254micro meters thick -> 10 mili inches
(SIGNAL T=35u L=2)
(DIELECTRIC T=254u)
(PLANE T=35u L=VCC)
(DIELECTRIC T=254u)
(PLANE T=35u L=GND)
(DIELECTRIC T=254u)
(SIGNAL T=35u L=3)
(DIELECTRIC T=254u)
(SIGNAL T=35u P=35u L=BOTTOM)
}
{DEVICES
(IC REF=U15 NAME=74ACT240.IBS L=BOTTOM)
(IC REF=U222 NAME=LCA3000.IBS L=TOP)
(IC REF=U17 NAME=F161.IBS L=TOP)
(R REF=R15 NAME=68 L=BOTTOM)
(R REF=R29 NAME=100 L=BOTTOM)
}
{PADSTACK=THR001, 0.03
(MDEF, 0, 0.06, 0.06, 0)
}
{PADSTACK=SMD001
(TOP, 1, 0.04, 0.06, 0)
}
{NET=IBIS_1
(PIN X=1.250c Y=0.950c R=U15.18 P=SMD001)
(SEG X1=1.250c Y1=0.950c X2=1.350c Y2=1.050c W=0.015c L=TOP)
(SEG X1=1.350c Y1=1.050c X2=1.600c Y2=1.050c W=0.015c L=TOP)
(VIA X=1.600 Y=1.050 L1=TOP L2=BOTTOM P=THR001)
(SEG X1=1.600 Y1=1.050 X2=1.650 Y2=1.100 W=0.015 L=BOTTOM)
(VIA X=1.650 Y=1.100 P=THR001)
(SEG X1=1.650 Y1=1.100 X2=1.650 Y2=1.150 W=0.015 L=TOP)
(PIN X=1.650 Y=1.150 R=R15.2 P=SMD001)
(SEG X1=1.650 Y1=1.150 X2=2.050 Y2=1.150 W=0.015 L=TOP)
(SEG X1=2.050 Y1=1.150 X2=2.050 Y2=1.050 W=0.015 L=TOP)
(VIA X=2.050 Y=1.050 L1=TOP L2=BOTTOM P=THR001)
(SEG X1=2.050 Y1=1.050 X2=2.050 Y2=2.500 W=0.015 L=2)
(VIA X=2.050 Y=2.500 L1=TOP L2=BOTTOM P=THR001)
(SEG X1=2.050 Y1=2.500 X2=2.150 Y2=2.600 W=0.015 L=TOP)
(PIN X=2.150 Y=2.600 R=U222.85 P=SMD001)
}
{NET=IBIS_2
(PIN X=4.600 Y=0.600 R=U17.2 P=THR001)
(SEG X1=4.600 Y1=0.600 X2=4.550 Y2=0.550 W=0.015 L=2)
(SEG X1=4.550 Y1=0.550 X2=4.200 Y2=0.550 W=0.015 L=2)
(SEG X1=4.200 Y1=0.550 X2=4.150 Y2=0.600 W=0.015 L=2)
(SEG X1=4.150 Y1=0.600 X2=4.150 Y2=1.350 W=0.015 L=2)
(VIA X=4.150 Y=1.350 L1=TOP L2=BOTTOM P=THR001)
(SEG X1=4.150 Y1=1.350 X2=4.150 Y2=1.500 W=0.015 L=TOP)
(SEG X1=4.150 Y1=1.500 X2=4.100 Y2=1.550 W=0.015 L=TOP)
(SEG X1=4.100 Y1=1.550 X2=2.350 Y2=1.550 W=0.015 L=TOP)
(SEG X1=2.350 Y1=1.550 X2=2.300 Y2=1.500 W=0.015 L=TOP)
(PIN X=2.300 Y=1.500 R=R29.1 P=THR001)
}
{END}
Have a great day...Kellee Crisafulli, HyperLynx Inc.
Received on Wed Nov 1 16:35:36 1995
This archive was generated by hypermail 2.1.8 : Fri Jun 03 2011 - 09:52:29 PDT