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Greg,
I will make an attempt to answer some of your questions.
1) To be more accurate, the requirement is -Vcc to +2*Vcc. There are two
reasons for this.
First, in an idealized situation, you can have a 100 % reflection at the
unterminated end of a transmission line. If you have a strong buffer driving it
(again in an ideal situation), it can switch a full swing (i.e. 5 volts to 0
volts). Under conditions like this it is possible to have a -5 volt undershoot
at the unterminated end (receiver). The amount of undershoot (or overshoot for
a rising edge) at the receiver will greatly depend on the clamping
characteristics of the input structure.
Second, different simulators extrapolate I-V curves differently (horizontally,
vertically, linearly, or any other way). The best way to ensure that the curve
is "correct" in the required range (-Vcc to +2*Vcc) is to define it.
Now, we all know that not all real devices can be measured all the way in this
range (even though I did succeed measuring some). However, you can do your best
in the lab and then extrapolate the curve to the required limits. Most often
these curves become a straight line because the resistive properties of the
diodes dominate their exponential nature beyond a certain voltaqe. If you
simulate this with a SPICE model, don't worry about hair splitting accuracy at
the limits. The point is to define something to the best of your knowledge that
otherwise might get messed up. However, I would recommend that the curve be
fairly accurate in the range of Vcc and GND +/- 1-2 volts, since most over and
undershoots could have such magnitudes.
On the other hand, if your SPICE model gives you kilo, Giga and Tera amp
currents at -1 to -2 or +6 to +7 volts for a 5 V device, you better make sure
that the resistive properties of the diodes and transistors are modeled
correctly in the SPICE model. If these are ignored, the defult number in SPICE
is usually 0 for the resistance, and the pure junction and channel current
equations can indeed yield currents in the kilo amp range already at -1 volts!
Real life measurements would give around 5-10 amps around -5 volts (~ couple of
Ohms slope).
For example the voltage in the exponential diode equation refers to the junction
voltage, which is not the same as the voltage at the terminals of the diode.
The current has to go through a significant chunk of resistive material before
it gets to the junctions where you are actually making you connection to the
device.
2) I don't know the answer to this one.
3) You can do that by "programming" what Lattice diagrams or Bergeron diagrams
do graphically. As far as how to construct these, you could probably find text
books or other literature (app notes in high speed logic data books) on the
subject. (I was born with this knowledge, so I am not sure where to find this
info... :-)
4) It was discussed in some of the IBIS Open Forum meetings, but I don't remeber
what the outcome was. Maybe someone else could answer that?
I hope I gave you some insight with this reply.
Arpad Muranyi
Intel Corporation
================================================================================
Anybody care to take a stab at these?
1. I was discussing IBIS model support with one of
our IC vendors, and they raised a concern about
ESD diode SPICE models not being accurate at
-5 V and + 10 V. Any clues about how to get
around this without setting up a test lab? Why
do you need such a wide range in the first place,
since nobody operates out there?
2. When will s2ibis 2.0 be available on Windows?
Actually, I'd be happy with DOS, but that's
probably not in the plan...
3. Has anybody written a "theory of operations"
paper on behavioral simulators? For instance, if
I have a simple behavioral driver model (no ESD
diodes, no package) driving a 50 Ohm transmission
line terminated at the far end into 50 Ohms, how
do I calculate the current and voltage vs. time at
the output of the driver? At the far end? This
must be an easy problem to solve. I'd like to
write a little C program to do this so I can better
understand IBIS and critically compare it to SPICE.
(For the sake of accuracy in system design issues,
not so I can write another simulator!)
4. Has anybody thought about organizing an IBIS
users group and mailing list?
Thanks in advance,
-- Greg Edlund +----+----+ Circuits and Modeling | | | Chen Systems Corp. < | ) 1414 W. Hamilton Ave. > ----- ) Eau Claire, WI 54701 < ----- ) voice (715) 833-7067 > | ) FAX (715) 833-7096 | | | email grege@chensys.com +----+----+ Text item: External Message Header The following mail header is for administrative use and may be ignored unless there are problems. ***IF THERE ARE PROBLEMS SAVE THESE HEADERS***. Subject: IBIS modeling questions From: grege@chensys.com (Greg Edlund) To: ibis@vhdl.org Content-Type: text/plain; charset="us-ascii" Mime-Version: 1.0 X-Mailer: Windows Eudora Version 2.0.3 X-Sender: gre@pop3.chensys.com Message-Id: <9511091901.AA06928@puma.chensys.com> Date: Thu, 9 Nov 95 13:01:50 -0600 Received: from [137.42.2.33] by puma.chensys.com via SMTP (931110.SGI/930416.SGI ) for @chensys.com:ibis@vhdl.org id AA06928; Thu, 9 Nov 95 13:01:50 -0600 Received: from puma.chensys.com by human.chensys.com (8.6.10/SMI-4.1) id TAA19046; Thu, 9 Nov 1995 19:12:10 GMT Received: from human.chensys.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA26170; Thu, 9 Nov 95 11:14:24 PST Received: from vhdl.vhdl.org by hermes.intel.com (5.65/10.0i); Thu, 9 Nov 95 11: 10:36 -0800 Received: from hermes.intel.com by relay.jf.intel.com with smtp (Smail3.1.28.1 #2) id m0tDcQ4-000twZC; Thu, 9 Nov 95 11:13 PSTReceived on Thu Nov 9 12:33:01 1995
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