Information on DIE, DIET, DCL, and EDIF PCB/MCM

-- [ From: Ron Christopher * EMC.Ver #2.10P ] --

I was asked to post information on DIE, DIET, DCL, and EDIF PCB/MCM to
the IBIS reflector. These are proposed standards that contain
information that relate to processing the higher level package.

DIE:
DIE is DIE Information Exchange Format. The specification states, "DIE
Format is a computer-sensible and human-readable interchange format for
information about unpackaged Integrated Circuits (ICs). . . The DIE
format conveys the physical and functional characteristics of an
unpackaged die; that is, those characteristics needed for place & route,
thermal analysis, electrical signal analysis, power distribution design,
physical bonding, behavior, test, and timing analysis. . . Die
specifically covered by the format are pre-diced die (wafer form), bare
die, and die that have been post-processed for pad attachment
mechanisms such as solder bump, wire bond, lead frame (TAB and Ribbon),
and Chips First."

DIE references IBIS for the IBIS information required for delay
calculation and signal integrity analysis. DIE references VHDL and
maps the physical pads to VHDL pins for the functional information.
DIE includes pad output driving capability at logic low level, pad
output driving capability at logic high level, and threshold voltages
required for testing and for voltage drop checking.

The specification states, "Passives, discretes, and Analog signal pin
electrical characteristics are not included in this draft. Some
bonding styles (Beam Lead and Solder Ball may not be fully covered yet.
MCM Substrate test development support and timing information are not
yet included." DIE does not include any physical characteristics of
the wire from the package lead down to the circuit.

The DIE specification is publicly available in several formats at
vhdl.org/pub/die/die1-0-3.* The work was done under an ARPA contract,
and EIA (Patti Rusher) is attempting to find a way to get it completed.

DIET:
DIET is Die Information Exchange for Timing. The DIET specification
states, "DIET Format is an unambiguous, EDA-tool processable, human-
readable medium for specifying and exchanging DC and AC timing
information such as setup, hold, and propagation delays about complex
IC components in either die or packaged form. . . The DIET Format
provides information about the external pin to pin timing
characteristics of complex digital or mixed-signal IC components -
there is no intent to represent timing information or functional
behavior about the internal gate level components or net list structure
of an IC. Neither does the DIET Format speak to instance or design
specific timing information regarding the IC's external environment."

The timing relationships include six basic types:
 - propagation delay - edge to value relationship
 - setup time - stable to edge relationship
 - hold time - edge to stable relationship
 - cycle time - edge to edge relationship
 - pulse width time - edge to edge relationship
 - skew time - edge to edge relationship.

DIET does include an internal timing point concept that supports static
timing with multiple clocks with one model. It supports multiple
versions in one table.

DIET does not include any expressive capability.

The DIET specification is publicly available in several formats at
vhdl.org/pub/diet/latest/diet0-95.* The work was done under an ARPA
contract, and EIA (Patti Rusher) is attempting to find a way to get it
completed. DIET could be contained in DCL which would then include
expressive capability.

DCL:
DCL is Delay Calculator Language being proposed by CFI/OVI to meet the
following requirements:

 - Allow silicon foundries to describe delay equations for ASIC
libraries, and in a single way which can be used by any set of CAD
applications and vendors.

 - Allow CAD vendors to interface to delay calculation for specified
design elements using a single interface to the foundry supplied
equations.

 - Account for wire capacitance as well as gate capacitance.

 - Provide a Delay Language compiler which creates a compiled form of
the delay expression language, which when executed with a specific net
description, can calculate all necessary delay characteristics of the
net and associated gates. This then provides the same set of delay
values to each vendor tool.

 - Provide a programming interface (PI) to a compiled form of delay
equations described in the delay equation expression language.

 - The calculation from the delay equations must be of high enough
performance to support both the batch calculation of all delays, and
the incremental calculation of individual nets within design
applications such as synthesis. This calculation is to include both
pre-layout and post-layout phases of the design process.

 - Support transmission line analysis.

The specification under development is publicly available in several
forms at cfi.org/public/Cfi/Development/Projects/Alr/DCLLang10_date
where date may keep changing. It is intended to be available in 1996.

EDIF PCB/MCM:
EDIF PCB/MCM 4.0.0 is an extension of EDIF to support all the physical
design detail of PCB boards, and MCM's. It is planned to be balloted
in 1995. The level 4.0.0 that includes MCM's will be available at the
end of October, 1995. It will be available in Frame format with
special login and password similar to the OMF specification. For
access contact Hilary Kahn at kahn@edif.org.
Received on Thu Oct 19 11:13:06 1995