Re: HERE IS: published circuit of non-monotonic output driver

I want to clarify the following regarding non monotonic curves:

1. In IBIS 2.1 you can specify non monotonic VI curves of the type referred to in Mark Johnson's email. IBIS specification is a data holder mechanism and as such does not preclude non monotonic data.

2. You can certainly use these curves "unaltered" in simulation. Convergence problems are certainly a possiblity, but then it is so for non linear simulation in general. So using these curves properly is the responsibility of the SIMULATION VENDOR.

I hope this helps.

C. Kumar
Cadence Design Systems
280 Billerica Rd
Chelmsford, MA 01824

508-262-6488
508-262-6600 (Fax)

> From jbrennan@VNET.IBM.COM Fri Sep 15 17:31:21 1995
> Return-Path: <jbrennan@VNET.IBM.COM>
> To: ibis@vhdl.org
> Subject: Re: HERE IS: published circuit of non-monotonic output driver
> In-Reply-To: Your message of Fri, 01 Sep 1995 17:22:58 PDT.
> <199509020022.RAA23496@netcom2.netcom.com>
> From: "John Brennan" <jbrennan@VNET.IBM.COM>
> Content-Length: 7401
> X-Lines: 166
>
>
> Sorry for the late reply.
>
> The note from Mark Johnson motivated me to do some digging and I found
> the following...
>
> The Petrovik(spelled Petrovick) paper refers to CMOS 4S/Hydra drivers,
> which were not the subject of my IBIS study. I have not seen their
> DC output IV curves. I suspect they would cause non-monotonic behavior
> like Phoenix.
>
> OMNI and Phoenix were designed after these drivers, and this compensation
> scheme was improved upon. There is a paper in 1993 CICC digest
> of papers(section 25, paper 5), that describes the driver compensation
> scheme used in Phoenix...
>
> Makoto Ueda, Allen Carl, et al, "A 3.3V ASIC for Mixed
> Voltage Applications with Shut Down Mode", IEEE
> 1993 Custom Integrated Circuits Conference,
> Digest of Technical Papers ("CICC-93"), pp. 25.5.1.
>
> I would like to point out that the nodes on the reference stacks
> between devices T11 and T12 are not connected(this caused problems).
> T12 Drain is tied to Vdd and T11 Drain is tied to GND. The shut off
> mechanism is provided by an extra transistor in the stack whose gate is
> fed from the output node via a half latch.
>
> In summary, the non-monotonic curves are created by a circuit of
> the form
>
> Vdd
> |
> --- IO
> | | | PAD----------
> A O---| | P | | |
> | | | | |
> --- --- |
> | Vgate | | | |
> O-----------------O-----------------------| | N | |
> | | | | | |
> --- | Vdd --- |
> | | | | | | |
> A O---| | N | | --- GND |
> | | | | | | | |
> --- | | P | |---O A |
> | | | | | |
> GND | --- |
> | | |
> | | |
> | | |
> | --- --------- |
> | | | | | Delay | |
> | | N | |-----| Buffer |----------
> | | | | | |
> --- --- ---------
> | | | |
> | N | |----O Vref
> | | | |
> --- ---
> | | | |
> GND | N | |---O Vdd
> | | |
> ---
> |
> GND
>
> where A is a control signal such as (data NOR user_enable_not). Just
> the simplified pull-down is shown above. During the transition,
> Vgate < Vdd
> is defined by the voltage stack reference voltage Vref. This voltage
> is larger at high Vdd and fast process conditions to minimize the
> driver performance window. This sets up the low Vgs at hi Vds curve in the
> IV curves for IBIS. When the transition is finishing(the worst
> di/dt region is past) the feedback delay buffer shuts off the
> stack and Vgate = Vdd(now Vds on big output decvice is small). This
> is the hi Vgs at low Vds curve. The IV curve also shows the transition region
> between the curves. The success of this scheme is highly dependent
> on the tuning of the transistors involved. As mentioned, care must
> be taken such that the stack shut off does not cause an impedance mismatch
> on the line that generates new reflections.
>
> Variations of this scheme were used in OMNI and Phoenix. So the answers
> to the $64K questions are 1.) yes and 2.) yes.
>
> John Brennan
>
> ************************************************************************
> John Brennan Internal: jbrennan@btv
> IBM Microelectronics Internet: jbrennan@vnet.ibm.com
> 862C / 1000 River Road Tel: 802-769-6982 (Tie-Line: 446)
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>
> ------------------ Referenced E-Mail ----------------------------
>
> Date: Fri, 01 Sep 1995 17:22:58 PDT
> To: ibis@vhdl.org, si-list@silab.Eng.Sun.COM
> From: mjohnson@netcom.com (Mark Johnson)
> Subject: HERE IS: published circuit of non-monotonic output driver
> Message-Id: <199509020022.RAA23496@netcom2.netcom.com>
> The schematic diagram of an output buffer which displays
> non monotonicity (measured at low frequencies, for
> example in a direct current I-V plot), is published in
> the following paper:
>
> J. Petrovik et al, "A 300k-Circuit ASIC Logic Family",
> 1990 International Solid State Circuits Conference,
> Digest of Technical Papers ("ISSCC-90"), pp. 88-89.
>
> Figure 6 of that paper shows a remarkably clever output
> driver circuit which compensates for process variations,
> supply voltage variations, and temperature variations.
> It performs this compensation better than any other circuit
> I've ever seen. (Quiz: but there's a cost; find the
> cost. Hint: it starts with the letter "p")
>
> If you put this output buffer on your curve tracer
> to measure the I-V curves, AND if you took more than
> 10 nanoseconds to move from one point on the curve
> to another point (i.e. if the A/D converter inside
> your curve tracer needs more than 10ns to settle),
> then you would see the exact I-V curve that Arpad
> Muranyi drew:
>
> >
> > *
> > * *
> > * * * * * * * * *
> > *
> > *
> > *
> >
>
> The region where the slope of the I-V curve goes negative
> (an incremental *negative resistance*, not usually felt to
> be the greatest thing in the world to hook up to a
> transmission line), is caused by the compensation circuitry.
> As Arpad hypothesized, there is indeed feedback in this
> output driver circuit. And, oh by the way, the circuit
> is symmetric; it has negative resistance in both its
> IOH-VOH curve and also in its IOL-VOL curve.
>
> Take a look at Figure 6 of the paper. Better yet, put it
> in your local SPICE simulator and simulate it "at speed"
> (transient) and also simulate a DC transfer curve. Don't
> believe me, I'm some random guy you've never met. Don't
> believe this message, it's just phosphor dots dancing on
> your CRT. Be self sufficient, try it yourself and
> make up your own mind.
>
> There are two $64,000 questions:
>
> 1. Does anybody actually _use_ circuits like Figure 6
> in real products?
>
> 2. When you run the thing at full speed (transient
> analysis), does it work OK?
>
> Final remark: the authors of this paper were from
> "IBM General Technology Division, Essex Junction,
> Vermont, USA".
>
>
> --Mark Johnson
>
>
Received on Mon Sep 18 07:07:27 1995