Use of IBIS

-- [ From: Ron Christopher * EMC.Ver #2.10P ] --

I understood IBIS is used as the circuit model to support delay
calculation which in turn supports static timing verification and/or
dynamic delay logic simulation. I know it is also used for noise
analysis or signal integrity.

I picked this up over on the CFI/OVI reflector.
" From all the EDA vendors that I know that are supporting IBIS, their
targte is not logic synthesis, it is not static timing analysis, it is
not logic simulation, it is not floorplanning, etc. IBIS is primarily a
modeling of the exterior of the Chip I/O targeted to support intra-chip
delays, noise, and waveform propagation."

Who are the vendors that support IBIS for static timing analysis and/or
logic simulation? I thought at least EPIC and Quad do. Am I correct,
and are there more?

Ron Christopher
Received on Tue Sep 19 13:48:10 1995