DATE: April 23, 1996
SUBJECT: 4/19/96 EIA IBIS Open Forum Minutes
VOTING MEMBERS AND 1996 PARTICIPANTS LIST:
AMP Hank Herrmann*
Cadence Design C. Kumar*
Contec CAE, Ltd. Dileep Divekar*, Norio Matsui
Cypress Bruce Wenniger
Hewlett Packard, EEsof Karl Kachigan, Henry Wu
HyperLynx Kellee Crisafulli
INCASES Olaf Rethmeier*
Intel Corporation Stephen Peters*, Will Hobbs*, Arpad Muranyi*,
John Keifer, Aaron Tang, Duane Quiet*,
Donald Telian, Jim Kruchowski
Interconnectix, Inc. Bob Ross*
Meta-Software (Les Spruiell)
Mitsubushi Tam Cao
Motorola Ahmed Omer*
National Semiconductor Syed Huq*, Donald Snyder, Chune-Sin Yeh
NCR (formerly ATT-GIS) Dave Moxley, Richard Mellitz
NEC (Hiroshi Matsumoto),
Quad Design Jon Powell, Chris Rokusek*
Quantic Labs (Mike Ventham)
Tanner Research, Inc. (Scott Wedge)
Texas Instruments Roger Cline, Ben Andresen, Sri Jandhyala,
Tareq Shahwan, Dan Phipps
Thomson-CSF/SCTF (Jean LeBrun)
UniCAD Canada Ltd. Celso Faia
VLSI Technology Dick Ulmer, Sung Oh*, Swami Gangadharan,
Daniel Kim, Tom Dockery
Zuken-Redac (John Berrie)
OTHER PARTICIPANTS IN 1996:
Alcatel John Fitzpatrick
Altera Vadim von Brzeski
Apteq Design System Dan FitzPatrick
Compaq Mark Leonard*
Digital Equipment Corp. Jeff Chu*
EIA Patti Rusher*
IC Works Eric Chen
Micron Technology Brian Johnson
MicroSim Ralph Perez
Molex Gus Panella*
North Carolina State U. (Michael Steer)
Oki Semiconductor Tom Chao
Rockwell Collins Thomas Thurman
S3, Inc. Sarathy Sribhashyam, Phap Duong
Seimans Nixdorf Arnaud Lacariere
Tektronix, Inc. Brock Hannibal
TRW & Free Model Foundation Robert Harrison
Veribest/Integraph Ian Dodd, David Wiens
Zeelan Technology George Opsahl
In the list above, attendees at the meeting are indicated by *. Principle
members or other active members who have not attended are in parentheses.
Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as
follows:
Date Bridge Number Reservation # Passcode
5/10/96 (916) 356-9200 2-66109 4323275
All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas out
7 days before each open forum and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by Will
Hobbs and give the reservation number and passcode.
NOTE: "AR" = Action Required.
-------------------------------- MINUTES -------------------------------------
INTRODUCTIONS
Gus Panella of Molex joined because of recent IBIS interest. Gus has been
involved for many years with electromagnetic extraction of connector model
information.
EIA MEMBERSHIP AND TREASURER'S REPORT
Patti Rusher received membership requests from Jeff Chu of Digital Equipment
and Ian Dodd of Veribest.
Patti Rusher estimated the treasury at $6000, with $2500 pending for DAC
participation. (After the meeting, Patti updated the actual number to be
$12,488.59. DAC booth participation expense reduces this to $9,988.59.)
MINUTES REPORT, MISC.
No Corrections.
MISCELLANY/ANNOUNCEMENTS
None.
PRESS AND WEB PAGE UPDATES
Patti Rusher has written a correction letter to EDN indicating that IBIS
has been formally ratified by EIA and ANSI.
NEW MODELS
Bob Ross reports that VLSI has submitted information to Michael Steer,
although it has not yet been posted on vhdl.org.
AR - Bob Ross investigate posting of VLSI information.
OPENS FOR NEW ISSUES
None.
EIA/IBIS 1996 MEMBERSHIP
Patti Rusher indicates about 5 or 6 outstanding invoices, although she has
to verify with accounting the most recent status.
AR - Bob Ross continue working with Patti Rusher to monitor the payment
for official EIA/IBIS Committee Membership.
DAC STANDARDS BOOTH
Patti Rusher is coordinating the booth with Jon Powell. It will have a
back-lit logo and poster. We still should send the 8-1/2" by 11" posters
with Velcro backing to Jon. You can also take them to DAC if you will be at
DAC the first day. Pat Manley, a graphics artist at the advertising agency
doing the other EIA work will create an electronic combination of logos.
Send electronic version of logos to
adgroup@aol.com
Patti received the IBIS bullet items information from Bob Ross for the
poster.
Since this is coordinated with Jon Powell, Patti and Jon need to work out
the exact process for the posters and communicate it to the reflector. (Also
pending are the "I Speak IBIS" badges.)
ANSI/EIA-656 PUBLICATION
Patti Rusher reports that the published version of ANSI/EIA-656 has been
sent to member companies. Several members have reported getting a copy.
AR - EIA/IBIS Members: if you have not received your copy, notify Patti.
DAC (DESIGN AUTOMATION CONFERENCE) MEETING ARRANGEMENTS AND AGENDA
Patti Rusher reports that Ron Werner is planning a Standards Roadmap
Birds of the Feather meeting on Thursday, June 6, 1996 between 6 PM and
8 PM. We will participate in this rather than doing our own BOF session
because IBIS is now quite well-known.
We will hold the DAC IBIS Meeting on Friday morning, June 7, 1996, and
allowing time for people to return that afternoon. Past DAC meetings have
been focused on ratification and administrative issues versus technical issues.
However, since we have only a few administrative issues and some pending
technical development, we probably will have some technical discussions.
We are seeking company sponsors for the meeting which usually involves
booking a room and providing some refreshments. Chris Rokusek of Quad
Design, Will Hobbs of Intel, and C. Kumar of Cadence all check on sponsoring
the Face-to-Face meeting. We estimate about 25 participants. A fallback
plan is to use IBIS funds.
AR - Chris Rokusek, Will Hobbs, and C. Kumar obtain closure by April 26
regarding hosting the meeting.
MODEL REWARD PROGRAM
Syed Huq reintroduced the program to reward companies which provide free,
public IBIS models. We decided to issue certificates of appreciation to
be presented at the IBIS meeting to the companies which provide such models
along with acknowledgment in a press release. This certificate would be
signed by EIA officers and Will Hobbs. Several organizations providing free
models and free utilities were mentioned.
Patti Rusher, Syed Huq, and Bob Ross will work off line to identify the
recipients.
Many IBIS models are also available through direct contact with companies.
Bob Ross is interested in identifying these contacts and publicizing them.
AR - Bob Ross post a request for anyone to submit possible contact people
who have IBIS models for distribution. Appropriate contacts for getting
IBIS models will be published on vhdl.org.
EIA WEB UPDATE
No change. Over 860 people have hit the page.
GOLDEN PARSER UPDATE
The Parser has been sent out. Patti Rusher has paid the submitted bill.
AR - Bob Ross will check out the new parser.
AR - Jon Powell create new executable and work with Bob to update the
information on vhdl.org.
SPICE TO IBIS VERSION 1.3
Bob Ross has put the new version on vhdl.org.
SPICE TO IBIS VERSION 2.1
Michael Steer reported privately that he will plan an upgrade.
AR - Bob Ross work with Michael Steer concerning the s2ibis2.1 upgrade.
EXPRESS ACTION ITEMS
Patti Rusher reports that ANSI/EIA-656 has been put forth for international
standardization under TC-93. An Express representation is required. The
pending EDIF 4 0 0 has an Express representation as does several other EDA
standards. Anyone within the IBIS community may propose doing an Express
representation. We are also seeking a proposal from Hilary Kahn from the
University of Manchester, UK, an Express expert who is familiar with IBIS.
DARPA funding may also be available for such a project.
AR - Patti Rusher request a proposal from Hilary Kahn and also copy Randy
Harr to inquire about the possibility of DARPA funding. [Done]
IBIS COMMENTS ON EDIF 3 9 9
Stephen Peters discussed the comments by David Wiens. Several vendors are
seriously considering interfacing to EDIF 4 0 0. The main concerns are
to have EDIF syntax to reference IBIS models and to reduce the redundant
ways to reference passive R, L, C components. The comments will be adopted
as an IBIS committee position. Patti Rusher wants the comments as early as
possible so that the EDIF technical group can move forward on them within the
introduction schedule. Patti also indicates that Hilary Kahn has a sample
PCB description that may be posted on the reflector.
AR - Stephen Peters work with David Wiens to finalize the response and
copy Patti Rusher and post the official comment on the Reflector.
BIRD31.1 - MATED MODELS
Bob Ross recapped the key points of BIRD31.1. The mated model will be in
a separate .mmf file and not in a .ibs file. BIRD31.1 will track any
approved package model development beyond BIRD28.3. BIRD31.1 is a two-terminal
syntax for similar capability. One addition is optional a pad capacitance.
Some reflector comments by Hank Herrman and David Fogel were noted.
The first point concerns Hank's proposal to add an edge rate parameter
to the mated model. His main point is that, unlike a package model which
is assumed to be associated with a particular die and therefore constructed
with correspondingly adequate detail, there is no way to determine the
intended performance limit of a mated model. If the edge rate is too fast,
the model may simulate too much ringing.
Bob Ross argued against the additions by stating these points: (1) There
already exists a required [Description] parameter where such information could
be presented in a manner similar to comment lines in Spice programs. (2) In
any case, simulators would not be able to do anything about non-compliance.
(3) There is no parallel counterpart for package models. (4) It is unclear
which limit to use - the largest time for which one "stage" would give
adequate limits, or the smallest time for which an infinitely distributed
stage would gives an accurate structure. Hank clarified that this would be
a model structure limit - the smallest time would apply before a more
complicated model would be appropriate.
After some more discussion and support by Gus Panella and Stephen Peters,
Bob agreed to add an edge rate specification subparameter.
The second point relates to defining the mated model physical limits. With
an edge card connector the circuit board fingers which could also have their
own ground plane extendions into the connector. The consensus was that
the mated model would end at the surface of the mated-model. The mated model
contains the optional C_pad1 and C_pad2 to provide an estimate of adjoining
PCB pad capacitances that are typically not within the mated model. Because
of historical evolution from the simplest L_pkg, R_pkg, C_pkg structures to
the more complicated coupled matrix models, the package model already provides
for such pad capacitances.
Stephen questioned whether the mated model should apply for sockets. IBIS
models for the Pentium Pro includes the socket within the package model.
When the socket is modeled as a mated model, the package parameters of the
device to be inserted into the socket may contain inappropriate, excessive
information. However, independent socket models are still needed. So we
agreed to continue including sockets within the mated model syntax.
Bob Ross will issue BIRD31.2 adding the edge rate limit parameter and
clarifying the mated model boundaries.
BIRD33 (EGG8) - PHYSICAL PACKAGE DISCUSSION
Stephen Peters reported that the package committee endorsed the EDIF 4 0 0
approach for physical representation. Future discussion will be on electrical
representations. Two possibilities include a Spice-like approach by C. Kumar
and a sement approach by Jon Powell. While syntactically different, these
approaches have similarities with respect to transmission line and nodal
structures. They both can handle general topologies which include forks and
possibly closed loops. Stephen indicated that handling ball grid array
packages with stub elements is a real necessity. He also has a proposal which
extends the existing BIRD28.3 structure to include forks and nodes.
The next meeting will be on Thursday, May 2, 1996.
BIRD34.1 (EGG9) - HANDLING STORED CHARGE
Bob Ross plans to send an HSPICE example which illustrates the BIRD34.1
proposal. Simulations of the equations in the proposal match the Spice diode
model simulations. C. Kumar advised Bob of a recent March, 1996 paper in the
IEEE Circuits and Systems Transactions on diode modeling including stored
charge effects.
EGG10 - PARSER ADDITIONS FOR NUMERICAL CHECKING
Chris Rokusek mentioned the two key items: A check is needed to assure that
the [Rising Waveform] and [Falling Waveform] voltage ranges for given fixture
provide ranges consistent with the V/I tables. Also, Stephen Peters proposes
a units check for realistic values - a common trap. Bob Ross pointed out that
this test needs to be based on actual values since the parser already process
the numerical information.
More time will be available at the next meeting for discussion.
NEXT MEETING:
The next telephone meeting is set for Friday, May 10, 1996.
==============================================================================
NOTES
IBIS CHAIR: Will Hobbs (503) 264-4369, Fax (503) 264-4210
will_hobbs@ccm.jf.intel.com
Server Chipset System Validation Manager, Intel Corp.
2111 NE 28th M/S JF1-57, Hillsboro, OR 97124 USA
VICE CHAIR: Jon Powell (805) 988-8250, Fax: (805) 988-8259
jonp@qdt.com
Transmission-Line Products Manager, Quad Design
1385 Del Norte Rd., Camarillo, CA 93010
SECRETARY: Bob Ross (503) 603-2523, fax (503) 639-3469
bob@icx.com
Modeling Engineer, Interconnectix, Inc.
10220 SW Nimbus Ave, K4, Portland, OR 97223
This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.
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To obtain general information about IBIS, to ask specific questions
for individual response, and to inquire about joining the EIA-IBIS
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Information on IBIS technical contents, IBIS participants, and actual
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use at trade shows.
==============================================================================
Received on Tue Apr 23 13:20:11 1996
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