Lies wrt clamp currents

Harish Patel (who is generating IBIS models for VLSI's standard
cell products) raised an interesting point. The clamp currents
that we extact or extrapolate from lab data go to totally
irrelevant values at +2Vdd or -Vdd, and probably aren't very
accurate anyway. Not that it really matters, since multi-amp
currents will never happen in a circuit that expects to remain
functional -- the actual maxima are more like Vdd/z0, or perhaps
100mA in most cases.

SO -- since we're engaging in fiction anyway it may as well
be a PLEASANT fiction. What lies can we tell that will best
suit simulator convergence algorithms? Presumably simulators
start out with the Thevenin voltages on the line and converge
to actual terminator currents; the shape of the clamp V/I
curve would affect convergence time.

How do we optimize this process outside of realistic operating
ranges?

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com