Stored Charge

Hello IBIS fans,

   I was reviewing the stored charge BIRD 34.1 . I have observed the
same glitch effect even with ESD diodes removed. So I think this glitch
is not just created by the stored charge in the diodes. This glitch can
easily be observed with a simple CMOS invertor with a fast (100 psec)
ramp as the input of the invertor, I think this glitch is because of the
stored charge in the depletion region of upper and lower devices.
  
   I will send a simple SPICE file that I have been using to simulate this
effect. The SPICE version which I am using runs into convergence problems
if I remove Cd1 capacitor. This capacitor presents the die capacitor in
IBIS models. After the simulation the voltage at node 2 should be probed.

Best Regards,
Peivand Tehrani.

**************************SPICE file************************

Driver Device Transitions For Gate Transition
*************************************************************
VDD 3 0 5
*************************************************************
M1 2 1 0 0 QN L=1.5E-6 W=136.4E-6
M2 2 1 3 3 QP L=1.5E-6 W=341E-6
*************************************************************
.MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 )
.MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200)
*************************************************************
VIN1 1 0 PULSE(5 0 0 .01n 0 100E-9 1E-3)
*************************************************************
Cd1 2 0 4p
R11 2 0 50
*************************************************************
.tran .001n 1n
.END
Received on Fri Jul 19 15:03:27 1996