Re[4]: R_Pad? and transistor diodes in HSPICE

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Scott and Sascha,

It is true that HSPICE does not have an independent parameter for the bulk
resistance that you would like to use for just the diode resistance. However,
you can get around that problem by inserting a discrete resistor between the
bulk node and whatever that connects to. This extra resistor will not effect
the currents through the channel, only through the diodes. This way you can
achieve a different value for the horizontal and vertical resistances.

Sascha, regarding your statement "huge extra expenditure to generate
IBIS models", I disagree. You, who want to make an IBIS model, shouldn't have
to fix the SPICE model first. That is the responsibility of those who make the
SPICE models (and all SPICE vs. IBIS advocates). What you need to decide is
whether you are going to take SPICE models or measured data for the basis of
your IBIS models.

Regarding the missing "IK (forward knee current) parameter", I can't comment,
you need to talk to your SPICE tool representative about that.

Scott, the above method (using an extra resistor in series with the bulk node)
might fix your problem, and then you won't have to "pull out" the diode from the
MOSFET model. However, that is your choice. If you feel you can model the
diode more accurately with an external diode, you can certainly do that.

Just as a side note, in an attempt to fix a similar problem on a third party
SPICE model, I couldn't add Drain and Source resistances, because those would
have altered the I-V curve in the operating region also (which were good to
start out with). Adding the bulk resistance didn't do the job fully either. So
I added a "behavioral half sided" resistor (along with a bulk resistor) which
acted as a short when the current was flowing in one direction, and acted as a
resistor when the current was flowing in the other direction. This way I could
avoid the modification of the I-V curve in the operating region, yet I fixed my
I-V curve in the clamping region. Here is the "half sided" resistor model:

**********************************************************************
.PARAM Res = 10
Eres Pos Neg VOL = 'min(0,I(Eres)*Res)'
**********************************************************************

I hope this helps,

Arpad Muranyi
Intel Corporation
================================================================================

Arpad,

I'm just a very beginner in IBIS modelling and I came across the
same problem Scott Schlachter rised up.
It was very kind if you could tell me how you handle this problem
or if I perhaps misunderstood something.

In your answer to Scott Schlachters question you wrote:

>If you have access to an HSPICE manual, look up the RD, RDC, RS,
>RSC, etc. parameters. Don't let yourself get confused that these
>are Drain and Source resistance numbers; the currents of parasitic
>diodes go through Drain, Source, and Bulk.

I think you are absolutely right when saying it is possible to correctly
model the resistance of the diodes. But there are some
problems with the HSPICE diode implementatation, anyhow.
RD, RDC, RSH ... specify the diode resistance. HSIPCE assumes the
currend through the drain-bulk diode (for instance) to flow the
same way as the drain-source currend does, so only one resistor
is used in the HSPICE model (I guess to simplify numerical algorithms).
Actually there are two differend resistances to take into account.

Rdrain decreases as gate width increases and increases as
HDIF+LD+LDD (contact to gate distance) increases but Rdiode
decreases as both parameters increase.

So I have to manually correlate every transistor diode params with
actual measurment.
If using only a few transistor types in gate arrays it is possible
but otherwise this will cause a huge extra expenditure to generate
IBIS models.

Additionally there is no IK (forward knee current) parameter;
neigther in ACM=0, 1, 2 nor 3. So it becomes impossible to model
low and high current charactristics correctly.

I was very pleased if you counceled me, much thanks in advance.

Kindest regards
Sascha Pawel

Arpad,

     In regard to RS, RD, and RSH, it appears that they are representing
only the horizontal resistance values associated with the transistor
(looking at a cutaway view of the transistor). This does not seem
like it is a reasonable resistance to use for the real diode current
path, as that path is more of a vertical path through the transistors
Drain, followed by a (largely) vertical path through the substrate
(N-transistor).
How accurate is RD for modeling the Drain resistance verticaly? Also, the
resistance through the substrate seems to be completely ignored. It just
seems to us at this point that pulling the diode out of the transistor
would be a better way to go (allowing for a more accurate diode
representation by having it be a seperate component). Under ACM=2, the
diode can be surpressed by setting IS, AD, and AS = 0.

Perhaps, though, we might be interpreting this model incorrectly. I look
forward to your feedback on this matter.

Regards,
-Scott Schlachter

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Subject: Re: Re[2]: R_Pad?
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