Re: Rising Waveform Loading Effects

Hi all,

Well Jon, I don't think we fundamentally disagree. It's more a matter of degree.
For instance, if I can hold tolerance of characteristic Z, losses, L and C of
vias, L and C of package pins, stability of power supplies, etc. to really
tight tolerances then I can make use of extremely accurate IBIS models which
have V@t curves which are derived into my known load. Unfortunately all these
other factors are extremely difficult to hold to tight tolerances. All I
was saying was that an IBIS model derived into a resistive load is probably
sufficient for most signal integrity work.

The current crop of IBIS models are a far cry from being accurate enough
to really predict the kinds of things Jon is talking about, but many of
them are good enough to ensure that I don't drastically mis-terminate
the transmission lines on my boards.

Another question to think about: do Ibis models derived from Spice models
really have the kind of accuracy that Jon needs?

Brock Hannibal
Design Engineer
Tektronix, Inc.

Jon Powell says,

>I must disagree with this statement. Though accurate transmission line
>characteristics are crucial for simulation, risetime and IV curve
>accuracy is also important. The IV curve vs line impedance directly
>determines the incident wave height (and thus incident switching and/or
>number of round-trips to switch) and crosstalk and overshoot are a
>function of risetime/falltime as much as line coupling and impedance.

>Brock Hannibal wrote:
>>
>> Hi all,
>>
>> Let me add a thought. Ed Boeckman asks:
>>
>> "I hope someone can help me to understand how the IBIS models will
>> accurately produce the correct physical response with an arbitrary but
>> realistic loading condition, different from the test fixture, at least
>> to a level of accuracy close to that which would result from the
>> original transistor level spice model, say within 5%."
>>
>> I've found that board level simulation accuracy is difficult to quantify
>> as a percentage number. There are a number of contributing factors such
>> as etch width and thickness variations along the length of the interconnect
>> line, cross-section variations(dielectric thickness), dielectric constant
>> variation with frequency, humidity, temperature, etc. Most FR-4 type boards
>> are themselves about 10% components. Holding the boards to a tighter tolerance
>> is both expensive and difficult.
>>
>> It turns out that if the IBIS model is derived into a nominal resistive
>> load that is representative of the transmission line characteristic
>> impedance that the dominant effect in the simulation is usually the
>> transmission line formed by the interconnect.
>>
>> I have verified this by actual measurement in a number of cases. This is
>> not to say that the model is irrelevant, only that the model's
>> output impedance curves and risetimes are not as critical as one might
>> think in predicting the performance of the system.
>>
Received on Mon Oct 28 18:14:12 1996