That is a relative check. I have seen models which do not settle to anything anything near the dc voltage. I mean the dc voltage defined by the VI table. (it should be the true dc , isn't it?). I think it is necessary explicitly clarify whether you are talking about dc voltage or steady state settling voltage.
> From owner-ibis@vhdl.vhdl.org Wed Oct 30 16:17 EST 1996
> Received-Date: Wed, 30 Oct 1996 16:17:17 -0500
> From: Chris Rokusek <crokusek@qdt.com>
> To: ibis@vhdl.org
> Subject: Egg10 Implementation
> Content-Type: text
> Content-Length: 1505
> X-Lines: 58
>
> Hi All,
>
> I've got a working version of ibischk2 that compares AC waveform
> endpoint voltages against the (DC) VI curves and the correspond test
> fixture.
>
> I need to define a tolerance of some sort to which the voltages agree.
> This relates to prior discussion of how long a waveform needs to
> settle. The spec does not provide a tolerence...
>
>
> Keywords: [Rising Waveform], [Falling Waveform]
> .
> .
> .
> A waveform table must include the entire waveform;
> i.e., the first entry (or entries) in a voltage column
> must be the DC voltage of the output before switching
> and the last entry (or entries) of the column must be
> the final DC value of the output after switching.
>
>
>
> I think we need to define a % voltage that the first/last entries must
> lie within (e.g. 2.0%).
>
> Percent of what, though? Well, how about percent of 0% to 100% of the
> waveform endpoint voltages difference itself. This would require a
> highly loaded waveform to settle to a more absolute voltage since it
> would have a smaller voltage swing. Is this a good thing?
>
>
> Also, this is easy to implement!! :)
>
>
> Example Waveform:
>
> Begins: (0ns, 0.0V)
> Ends: (9ns, 4.0V)
> Load: 50 Ohms, 0.0V
>
>
> For 2% agreement, the v_tolerance = 2% * (4.0 - 0) = .08V
>
> So model passes if...
>
> -0.08 < v_dc_low_for_load < 0.08
>
> AND
>
> 3.92 < v_dc_high_for_load < 4.28
>
>
> Is this reasonable?
>
> -Chris R.
>
>
>
Received on Thu Oct 31 10:15:22 1996
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