EIAJ I/O Interface Model

I just wanted to follow up on Bob Ross's posting.
Our sister company Applied Simulation Technology, Ltd., Japan
is a member of the EIAJ I/O Interface Modeling Project Group.
I have received the following short summary of the specification.

EIAJ I/O Interface Model Summary
1) Model Coverage
The model is not expressed as electrical characteristics at pins of IC package,
but expressed as a network including internal circuits of package and I/O
buffers.
2) Model Description
The model is described as a circuit composed of electrical components
and interconnections in SPICE format. This allows the description of
ground/power circuits, complex structures of packages and modules.
3) Accurate Simulation
Signals are added at input nodes of internal buffer circuits. This
allows for accurate simulation by covering from internal buffer
circuits to external load circuits.
4) Device Models
Nonlinear device characteristics are described by 1- 2- or 3-dimensional
tables. However, models such as SPICE may be used if IC companies like.
5) Separation of data of IC, Package and Module
The data of IC, package and module are stored separately. It allows to
make and supply data of IC, package and module independently.
6) Application Frequency
The circuits of the model should be changed according to application
frequency. The model can accomodate multiple model circuits for
different application frequencies.
7) EMI Simulation
Package data will be extended to include material and 3-dimensional
shapes for accurate EMI simulation in the future.
8) Relation with IBIS
The model is extended from IBIS for more complicated application.
Both models might be used according to applications. Translators
between both models might be developed.

 
Received on Wed Feb 12 18:40:28 1997