Re: Bird 36.2

Hello David:

     My comments below, prefixed with >>>

                 Regards,
                 Stephen Peters
                 Intel Corp.

Questions regarding Bird 36.2,

1. How do you specify vias (thru or blind) or pads that add additional
capacitance to a trace, like test pads?

>>> If I understand your question properly, a via or pad can
             be specified as a C or L/C in the path just like any other
             element. For example

             [Path Description] example
             J1
             Len = 1.0 C=2.5p L=1.0n \ | a lenght of trace
             Len = 0 C= 0.5p \ | a via
             Len = 0.7 C=2.0p L=2.0n \ | a second length of trace on a
                                           | different layer

2. How do you specify tolerances for all the parameters in Bird 36.2?
Nominal values may not be sufficient for doing a thorough SI analysis.

>>> Good point. Currently there is no way to specify a
              tolerance for the L/R/C parameters of a section.
              I would suggest that if you have 'min' and 'max' Zo/Tpd
              parameters for the board then several different .edb file could
              be provided.
              (As an aside, I wonder if PC boards really have 'min' and 'max'
              corners as with a silicon I/O buffer, or if accounting for
              board variations is something that is handeled in the simulator
              itself via some statistical (Monto Carlo) analysis. Comments?)

David Fogel

 
Received on Wed Mar 12 08:56:33 1997