IBIS BIRD51 3-STATE_ECL

IBIS folks:

BIRD51 adds the 3-state_ECL Model type. A few ECL devices are designed
with a true high-Z mode.

Bob Ross
Interconnectix/Mentor Graphics

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BIRD ID#: 51
ISSUE TITLE: 3-state_ECL
REQUESTER: Bob Ross, Mentor Graphics
DATE SUBMITTED: 5/1/98
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

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STATEMENT OF THE ISSUE:

A true 3-state ECL device cannot be described correctly using IBIS.

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STATEMENT OF THE RESOLVED SPECIFICATIONS:

The [Model] keyword is shown with changes indicated by the |* lines below:

|==============================================================================
| Keyword: [Model]
| Required: Yes
| Description: Used to define a model, and its attributes.
| Sub-Params: Model_type, Polarity, Enable, Vinl, Vinh, C_comp, Vmeas, Cref,
| Rref, Vref
| Usage Rules: Each model type must begin with the keyword [Model]. The
| The model name must match the one that is listed under
| [Pin] or [Series Pin Mapping] keyword and must not contain
| more than 20 characters. A .ibs file must contain enough
| [Model] keywords to cover all of the model names specified
| under the [Pin] and [Series Pin Mapping] keywords, except
| for those model names that use reserved words (POWER, GND and
| NC). Model names with reserved words are an exception and
| they do not have to have a corresponding [Model] keyword.
|
| Model_type must be one of the following:
|
| Input, Output, I/O, 3-state, Open_drain, I/O_open_drain,
| Open_sink, I/O_open_sink, Open_source, I/O_open_source,
|* Input_ECL, Output_ECL, I/O_ECL, 3-state_ECL, Terminator,
|* Series, and Series_switch.
|
| Special usage rules apply to the following. Some definitions
| are included for clarification:
|
| Input These model types must have Vinl and Vinh
| I/O defined. If they are not defined, the
| I/O_open_drain parser issues a warning and the default
| I/O_open_sink values of Vinl = 0.8 V and Vinh = 2.0 V are
| I/O_open_source assumed.
|
| Input_ECL These model types must have Vinl and Vinh
| I/O_ECL defined. If they are not defined, the
| parser issues a warning and the default
| values of Vinl = -1.475 V and Vinh =
| -1.165 V are assumed.
|
| Terminator This model type is an input-only model
| that can have analog loading effects on the
| circuit being simulated but has no digital
| logic thresholds. Examples of Terminators
| are: capacitors, termination diodes, and
| pullup resistors.
|
| Output This model type indicates that an output
| always sources and/or sinks current and
| cannot be disabled.
|
| 3-state This model type indicates that an output
| can be disabled, i.e. put into a high
| impedance state.
|
| Open_sink These model types indicate that the output
| Open_drain has an OPEN side (do not use the [Pullup]
| keyword, or if it must be used, set I =
| 0 mA for all voltages specified) and the
| output SINKS current. Open_drain model
| type is retained for backward
| compatibility.
|
| Open_source This model type indicates that the output
| has an OPEN side (do not use the [Pulldown]
| keyword, or if it must be used, set I =
| 0 mA for all voltages specified) and the
| output SOURCES current.
|
| Input_ECL These model types specify that the model
| Output_ECL represents an ECL type logic that follows
| I/O_ECL different conventions for the [Pulldown]
|* 3-state_ECL keyword.
|
| Series This model type is for series models that
| can be described by [R Series], [L Series],
| [Rl Series], [C Series], [Lc Series],
| [Rc Series], [Series Current] and [Series
| MOSFET] keywords
|
| Series_switch This model type is for series switch
| models that can described by [On], [Off],
| [R Series], [L Series], [Rl Series],
| [C Series], [Lc Series], [Rc Series],
| [Series Current] and [Series MOSFET]
| keywords
|
| The Model_type and C_comp subparameters are required. The
| Polarity, Enable, Vinl, Vinh, Vmeas, Cref, Rref, and Vref
| subparameters are optional. C_comp defines the silicon die
| capacitance. This value should not include the capacitance of
| the package. C_comp is allowed to use "NA" for the min and
| max values only. The Polarity subparameter can be defined as
| either Non-Inverting or Inverting, and the Enable subparameter
| can be defined as either Active-High or Active-Low.
|
| The Cref and Rref subparameters correspond to the test load
| that the semiconductor vendor uses when specifying the
| propagation delay and/or output switching time of the model.
| The Vmeas subparameter is the reference voltage level that the
| semiconductor vendor uses for the model. Include Cref, Rref,
| and Vmeas information to facilitate board-level timing
| simulation. The assumed connections for Cref, Rref, and Vref
| are shown in the following diagram:
|
| _________
| | |
| | |\ | Rref
| |Driver| \|------o----/\/\/\----o Vref
| | | /| |
| | |/ | === Cref
| |_________| |
| |
| GND
|
| Other Notes: A complete [Model] description normally contains the following
| keywords: [Voltage Range], [Pullup], [Pulldown], [GND Clamp],
| [POWER Clamp], and [Ramp]. A Terminator model uses one or
| more of the [Rgnd], [Rpower], [Rac], and [Cac]. However, some
| models may have only a subset of these keywords. For example,
| an input structure normally only needs the [Voltage Range],
| [GND Clamp], and possibly the [POWER Clamp] keywords. If one
| or more of [Rgnd], [Rpower], [Rac], and [Cac] keywords are
| used, then the Model_type must be Terminator.
|-----------------------------------------------------------------------------
| Signals CLK1, CLK2,... | Optional signal list, if desired
[Model] Clockbuffer
Model_type I/O
Polarity Non-Inverting
Enable Active-High
Vinl = 0.8V | input logic "low" DC voltage, if any
Vinh = 2.0V | input logic "high" DC voltage, if any
Vmeas = 1.5V | Reference voltage for timing measurements
Cref = 50pF | Timing specification test load capacitance value
Rref = 500 | Timing specification test load resistance value
Vref = 0 | Timing specification test load voltage
| variable typ min max
C_comp 12.0pF 10.0pF 15.0pF
|
|=============================================================================

In the NOTES ON DATA DERIVATION Section, change section 3b) for Ramp Rates
to read (Change noted by the |* line):

| 3) Ramp Rates:
| The following steps assume that the default load resistance of 50 ohms is
| used. There may be models that will not drive a load of only 50 ohms
| into any useful level of dynamics. In these cases, use the semiconductor
| vendor's suggested (nonreactive) load and add the load subparameter to
| the [Ramp] specification.
|
| The ramp rate does not include packaging but does include the effects of
| the C_comp parameter; it is the intrinsic output stage rise and fall time
| only.
|
| The ramp rates (listed in AC characteristics below) should be derived as
| follows:
|
| a. If starting with the silicon model, remove all packaging. If starting
| with a packaged model, perform the measurements as outlined below.
| Then use whatever techniques are appropriate to derive the actual,
| unloaded rise and fall times.
|
| b. If: The Model_type is one of the following: Output, I/O, or 3-state
| (not open or ECL types);
| Then: Attach a 50 ohm resistor to GND to derive the rising edge
| ramp. Attach a 50 ohm resistor to POWER to derive the
| falling edge ramp.
|
|* If: The Model_type is Output_ECL, I/O_ECL, 3-state_ECL;
| Then: Attach a 50 ohm resistor to the termination voltage
| (Vterm = VCC - 2 V). Use this load to derive both the
| rising and falling edges.
|
| If: The Model_type is either an Open_sink type or Open_drain type;
| Then: Attach either a 50 ohm resistor or the semiconductor vendor
| suggested termination resistance to either POWER or the
| suggested termination voltage. Use this load to derive both
| the rising and falling edges.
|
| If: The Model_type is an Open_source type;
| Then: Attach either a 50 ohm resistor or the semiconductor vendor
| suggested termination resistance to either GND or the
| suggested termination voltage. Use this load to derive both
| the rising and falling edges.
|

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ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

The National Semiconductor 100316 has true 3-state_ECL pins. Several other
ECL devices with a true high-Z state also exist. They currently have to
be described incorrectly as Output_ECL models - ignoring the high impedance
state, or as I/O_ECL models - requiring incorrect Vinl and Vinh threshold
information which would not be used. The only correct solution is proposed
in BIRD51 to define the new 3-state_ECL model type

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ANY OTHER BACKGROUND INFORMATION:

Tom Dagostino for pointing out the problem devices and the need for the IBIS
IBIS document to include the 3-state_ECL model type.

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Received on Fri May 1 17:29:16 1998