To All:
This is a reminder to for those planning to attend the December 7, 1998
IBIS SUMMIT MEETING and JEDEC JC-16.2 and JC-42 MEETINGS to sign up.
You can also sign up through the Upcoming Events Link on the IBIS home
page.
Bob Ross
Mentor Graphics.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------
****************** REMINDER NOTICE ********************
-------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------
IBIS/JEDEC SUMMIT CALL FOR PARTICIPATION, PRESENTATIONS
-------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I B I S S U M M I T M E E T I N G
Time/Date: 12:00 PM - 5:00 PM, Monday, December 7, 1998
Location: Kona Kai Continental Hotel
1551 Shelter Island Drive
San Diego, CA 92106-3102
Tel: 619-221-8000
Fax: 619-221-5953
Content: Interchange of ideas with JEDEC JC16.2 Subcommittee on
Modeling and Test
Purpose: Solicit and Exchange IBIS Model Related Information and Ideas.
Sponsors: EIA
Contact for Signup for IBIS Meeting and FREE Buffet Lunch:
Patti Rusher
pattir@eia.org
J E D E C M E E T I N G S
Time/Date: 8:00 AM - 5 PM, Tuesday, December 8, 1998
Content: IBIS Participants are invited to the JEDEC JC16.2 meeting
also to view and discuss issues of mutual concern. You must
signup for these meetings to be formally invited.
Schedule of Meetings:
JC16.2 - Modeling and Test: Tuesday Morning, December 8, 1998
JC42 - Memories: Tuesday Afternoon, December 8, 1998
Deadline: JEDEC Meeting Registration Deadline is November 11, 1998
Contact for Signup to JEDEC Meeting:
Patti Rusher
pattir@eia.org
URL for JC42 Schedule: http://www.jedec.org
BACKGROUND
The JEDEC committee is involved in standardization activities from the
physical device point of view. D.C. Sessions of VLSI Technology has been
active in both JEDEC JC16.2 and the EIA IBIS Open Forum. The joint/co-
located meeting offers several opportunities: EDA people can understand
some real device modeling and testing concerns and the semiconductor
people can understand the applicability of IBIS models and corresponding
simulation tools.
The IBIS format is being considered as the template for a JEDEC data sheet
proposal. The proposal is to provide the envelope tables and data
for the I/O characteristics and pin capacitance for SSTL2 related
specifications. Interaction with IBIS experts will be very helpful.
The IBIS meeting will be conducted as a formal IBIS Summit meeting.
Presentations are expected to be available and archived in an electronic
format, and minutes of the meeting will be issued. Any pending formal
decisions (votes) will be announced at least two weeks prior to the meeting.
JEDEC MEMBERS ARE INVITED TO PROVIDE PRESENTATIONS ON CURRENT TECHNOLOGIES
SUCH AS SSTL AND HSTL, ETC., AND ASSOCIATED MODELING/SIMULATION ISSUES TO
THE IBIS SUMMIT MEETING TO PROMOTE INTERACTION AMONG TECHNICAL EXPERTS.
CALL FOR PRESENTATIONS
We are seeking presentations from individuals who have IBIS experiences
or issues.
Format of Presentation: Overhead Projections
Time: 15-30 Minutes
Electronic Archival: We request electronic versions so that the
presentations can be archived and also made
available to non-attendees. Formats used in
the past have been text, Power Point, Word,
Postscript, and Acrobat. Plan to bring about
30 copies for distribution at the meeting.
If you plan a presentation, please supply
Title:
Presenter:
E-mail address:
Company:
Telephone:
Estimate Time:
Send this to:
Bob Ross
bob_ross@mentorg.com
AGENDA
The agenda includes presentations, discussions, a break, and a luncheon
(which will be provided). In addition, we will have an opportunity for
Ad Hoc presentations.
Received on Wed Nov 11 10:45:02 1998
This archive was generated by hypermail 2.1.8 : Fri Jun 03 2011 - 09:52:30 PDT