Re: Question about IBIS 3.2 EBD specification

Hi Ian, all,

I brought some of these items up previously.

1) .EBD was proposed and selected as a an electrical only specification for
use
   modeling modules with IC's and was specifically set to support a single
   connector which is all that is needed to model most CPU and memory modules.
   This is intended to handle a very limited number of cases and only has
   uncoupled models. The committee at the time stated that physical PCB files
   should be used to handle the more complex cases.
   So to answer your first question unless someone else knows better I
don't believe
   you can have more than one connector. I agree multiple connectors seems a
   logical extension.

Other background:
   Originally I wanted to create a more flexible PCB like specification
   we could use. This would address most of the issues you mentioned
   about planes etc. I proposed a simple one that was narrowly voted down.
   The EDIF specification was endorsed instead and we asked the EDIF
   group to add a few IBIS keywords which I believe they did. The
   problem with EDIF is it is still not a universal standard that comes with
   all PCB tools (EDIF writer is not a standard output from all the PCB tools
   and it is very complex to implement).

3) I asked the same question on loops about 6 months ago and the resolution
   as I recall was that a zero ohm resistor could be used if needed to
   jump it back in a loop condition.

best wishes...
Kellee

At 05:47 PM 8/3/99 -0500, Dodd, Ian wrote:
>Hi,
>
>We have a number of questions regarding the EBD section of the IBIS 3.2
>specification.
>
>1. How does one create an EDB [Pin List] for a layout that has multiple
>connectors?
>
>The example in the specification seems to assume a single connector:
>
>[Pin List] signal_name
>A1 GND
>A2 data1
>e.t.c.
>
>It seems to us, that it would be logical to extend this to multiple
>connectors:
>
>Pin List] signal_name
>J1.A1 GND
>J1.A2 data1
>e.t.c.
>
>J2.B1 data33
>J2.B2 data34
>e.t.c.
>
>The problem here is that there is an 8 character limitation on the pin name,
>which
>would include the layout reference designator, the separator and the layout
>pin name,
>which together would make up the EDB pin name.
>
>2. In order to simulate a signal net, the tool needs to go into the IBIS
>model and get the
>supply/reference pins. It then needs to find which connector pin is wired to
>those pins.
>(to figure out what supply voltages are being used)
>If the EDB layout has supply traces, I would expect this connectivity to be
>shown in
>the Path Description section, however what is done to show connectivity
>through a
>plane? Does the plane need to have an entry in the connectivity section
>(possibly with
>dummy zero length sections) ?
>
>3 The EBD connectivity section appears to not allow for the description of
>traces with loops.
>If this is true, does this need to be spelled out.? Is the lack of support
>for traces with loops
>an issue? (Our PCB CAD system can certainly be forced into creating looped
>traces - it will
>warn you but it can be done!)
>
> Thanks
> Ian Dodd
>
>
>> Ian C Dodd
>> Technical Manager, Signal Integrity Products
>VeriBest, Inc. Boulder CO USA
>EMAIL: idodd@veribest.com
>PHONE: (303) 581-2358
>
>
>
>
>
>
>
>
---------------------------------------------------------
Have a great day....
Kellee Crisafulli
HyperLynx, a division of Pads Software Inc.
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:   <http://www.hyperlynx.com>
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Received on Tue Aug 3 17:57:07 1999