RE: IBIS BIRD59 MODEL SPEC DIAGRAMS

Al,

Just some quick comments, not sure I'm actually answering all/any of your
questions...

My understanding of Vinl and Vinh is that they are meant to cover process
corners of the device. A given device will "switch" when a signal cross
some single voltage (ignore slew rate effects for now!!) that lies between
Vinl and Vinh. The designer shouldn't really need to care about that exact
voltage. Some devices will transition earlier than others even though they
have the exact same Vinl, Vinh specification. This variation causes timing
delay values to require both a MIN and MAX value (e.g. MIN on a rising edge
corresponds to the signal rising above the Vinl and the MAX of this rising
edge is when the signal crosses above the Vinh).

Now enter hysteresis. When a receiver is said to have hysteresis, that just
means that it can adjust both of these thresholds based on its previous
logic state--sort of like is has memory. The voltage thresholds can be
shifted farther OR closer to the current state's DC level depending on
whether the designer wants larger noise (crosstalk, reflection) tolerance
(farther), vs. faster delay's (closer).

Be aware that there are even more complicated methods of specifying input
thresholds using min/max slew rate and voltage thresholds that are not
currently covered by IBIS as well. More work for us later on I guess...

Hope that helps some!

Chris Rokusek
Viewlogic Systems

> -----Original Message-----
> From: Al Davis [mailto:aldavis@ieee.org]
> Sent: Friday, August 06, 1999 10:12 AM
> To: ibis@eda.org
> Subject: Re: IBIS BIRD59 MODEL SPEC DIAGRAMS
>
>
>
> I still find the descriptions to be confusing.
>
> The [Model Spec] group seems to have the purpose of describing how the
> analog representation of a waveform is interpreted as digital,
> evaluating its logic state and quality.
>
> My original interpretation of the old (pre model spec) Vinl and Vinh
> is as follows:
>
> The logic value switches from a "logic low" to a "logic high" when a
> rising signal crosses through Vinh. It switches from "logic high" to
> "logic low" when a falling signal crosses through Vinl.
>
> In a static sense, a voltage below Vinl indicates a "logic low" state,
> above Vinh indicates a "logic high" state, and between is unknown, in
> transition.
>
> On further reading, I believe this may not be the proper
> interpretation.
>
> Other parts of the spec lead me to believe that the intended
> interpretation is:
>
> The logic value switches from a "logic low" to a "logic high" when a
> rising signal crosses through Vinl. It switches from "logic high" to
> "logic low" when a falling signal crosses through Vinh.
>
> Note interchange of Vinl and Vinh, compared to above. This seems
> illogical to me, but clarifies (sort of) some of the other
> parameters, and fits with the note on how to "mimic a hysteresis
> effect" using only Vinl and Vinh.
>
> Another interpretation could be:
>
> The logic value switches from a logic low to "rising" when a
> rising signal crosses through Vinl, then finally switches to logic
> high on crossing Vinh. It switches from logic high to "falling" when
> a falling signal crosses through Vinh, then switched to "logic low" on
> crossing Vinl.
>
> This adds the notion of an in-transition state, when the logic state
> is neither high nor low, and possibly creates a use for the new
> hysteresis parameters.
>
> The composite (with the new hysteresis parameters) could be
> interpreted as ......
>
> The logic value switches from a "logic low" to "rising" when a rising
> signal crosses through Vinl
>
>
>
> Now, add "[Model Spec]" ....
>
> It, too, has a Vinh and Vinl, this time with a min and max. I wonder
> why it is necessary to have it twice. Why not just add optional min
> and max fields to the original? or move the existing parameters to be
> under ModelSpec, for consistency? The same applies to Vmeas.
>
> It is still not clear what the hysteresis parameters do. It appears
> to me that hysteresis can be adequately described without the new
> parameters. What actually happens at Vinh+, Vinh- ? How does this +
> and - differ from the min and max columns? This is still not clear.
>
> --------------------
>
> On the "overshoot" parameters ......
>
> Add:
>
> The purpose of the "overshoot" and "pulse" groups of parameters is to
> determine the quality of an incoming signal.
>
> A signal is considered to be "bad quality" if:
>
> 1. V ever exceeds D_overshoot_high
> 2. V ever drops below D_overshoot_low
> 3. V exceeds S_overshoot_high longer than D_overshoot_time
> 4. V drops below S_overshoot_low longer than D_overshoot_time
>
> --------------
>
> the "pulse" parameters ....
>
> The wording is still unclear. The words and picture conflict with
> each other, probably because of the confused interpretation of Vinh
> and Vinl.
>
Received on Fri Aug 6 16:57:34 1999