Re: BIRD #61 -- Characterization of Receivers

Please note that I've trimmed the distribution to the standards list.
Presumably there is a difference between the standards list and the
users list, and this falls across that line.

Lynne Green wrote:
>
> >>
> A NEGATIVE delay is possible for ANY logic circuit. Example: a simple inverter,
> with its threshold at any level except exactly Vcc/2. Apply a slow ramp, and
> measure the 50% to 50% delay. It will be negative for either the rising or
> falling edge (depending on whether the threshold was under/over Vcc/2).
> This happens because logic gates switch when they reach a voltage threshold
> determined by transistor sizing.
>
> While I would not expect a negative delay for most I/O, it is certainly not
> forbidden at light loading. And a negative increment in delay is almost certain
> at light loading, as pointed out by others.

Welcome to the debate.

The question is: do you or any of the the other algorithm troglodytes
have comments on the feasibility of implementing input delay models
based on the table scheme we presented?

We really care -- honestly.

-- 
D. C. Sessions
dc.sessions@vlsi.com