JEDEC JC-16 news

I got back just a bit late to join the conference call this morning.
Anyway, JEDEC's memory-related committees met this week, including
JC-16 (which is more or less tasked with signal-integrity issues
including modeling.) A few of the high points:

1. JC-16.2 will be organizing a collection of subsystem models
        for use in evaluating proposed new interfaces.
2. Return-path effects (SSO, jitter) are the primary limiters
        on DDR-II performance.
3. JC-16 needs to use IBIS to specify permitted I/O behavior.
        A working group will meet to address the use of IBIS for
        standards specification the day after the DesignCon IBIS
        summit in the Bay Area (Tues 1 Feb). It is hoped that DC
        won't be the only IBIS member present.
4. It looks like JEDEC will be reorganizing the website to
        make thiings easier to find. Unless you're all a lot
        smarter than I am, this is welcome news indeed.
5. New chair of JC-16: D C Sessions

-- 
D. C. Sessions
dc.sessions@vlsi.com