Re: IBIS Questions

Hello John:

   My comments are below.

  Regards,
  Stephen Peters
  Intel Corp.

> Hi,
>
> I had several questions regarding IBIS.
>
> 1) Is IBIS able to model SSTL2 and SSTL3?
> 2) Our company has created I/Os that are proprietary. They are
> differential. They also need to be AC coupled. As a result,
> series capacitors must be placed between the driver and receiver.
> Our I/Os are designed to drive and receive A.C. PECL signals. Can
> IBIS be used to model these I/Os? The D.C. levels of our drivers
> are not PECL levels.

I'm not real familiar with A.C. coupled P/ECL(?), but as long as you can
extract DC I/V curves for both states and V/T curves switching into a
representative non-reactive load, then you should be able to extract
reasonable IBIS data that a simulator can then turn into a model.

> 3) Can't IBIS model any I/O since it just utilizes I-V curves? Is
> the question regarding generating IBIS models just a question
> regarding how many I-V tables need to be generated and the loading conditions
> when generating the "Rising and Falling Waveform"? Is this why IBIS
> can support only certain I/Os (TTL, ECL, etc).

  Basicly, yes. Although, in fairness, IBIS can describe most any currently
available I/O structure.

> 4) Isn't the "Ramp" data and the "Rising and Falling Waveform" redundant?
> Aren't both used to determine rise and fall times?

  The Ramp data was the used for specifying ramp times in IBIS ver 1.1 models
but it has been superseded by the Rising and Falling Waveform data (for IBIS
ver 2.1 and above). "Ramp" is retained only for backwards compatibility. If
the Waveform data is available then most all simulators will choose this over
the Ramp data as the Waveform data leads to a better model.

> 5) Since IBIS uses I-V curves, can it model transient or hysteresis effects
> of drivers and receivers? For example, if a driver initially drives
> 6 ma at 2 volts (logic high). After the driver stabilizes at the
> logic high (2 volt), then it drives .05 ma. It seems IBIS can't model
> this type of driver. Is this true? I assume that is why all packaging
> elements(capacitors and inductors) must be separated from the output driver.
>

  Well, first I would say that if an IBIS data sheet contains I/V or V/T data
that is non-monotonic, multi-valued, or otherwise 'ill-behaved', then I would
not expect a simulator to turn that data into a usable model. However, given
your description, it sounds like the driver above can be modeled by using the
[Driver Schedule] keyword. This keyword, in effect, allows one to switch in
our out multiple I/V and V/T curves, and is included specifically to model
drivers with multiple output stages (which is what it sounds like you have).
This keyword is available in IBIS ver3.1. Of course, your simulator must also
support this keyword -- check with your vendor.

I'm not sure what you mean by the statement "all packaging elements must be
separated fro the output driver" Are you referring to the on-die power and
ground distribution network to the buffer and how gnd bounce and/or rail
collapse effects the V/T curves?

> 6) Are there any good books or documents on IBIS, how it works, and how to
> create accurate IBIS models?

  The IBIS Cookbook is probably the most comprehensive guide available on
making IBIS models -- it is available on the IBIS website at
http://www.eia.org/eig/ibis/tools.htm (bottom of the page). I also suggest
contacting your simulation software vendor, especially is you have specific
questions about how a particular keyword is used, or what data works best for
a specific driver and application.

> 7) Is there anything preventing IBIS from accurately modeling high speed
> circuits (rise/fall times=100 ps)?

Well, depends on what your requirements are for 'accuaracy'. As far as the
basic behavioral description of a driver goes, I belive I/V and V/T
descriptions can produce simulation results that are within the 10s of PS of
detailed transistor level models. However, there are other effects, external
to the driver itself, that must be accounted for -- specifically SSO effects
(i.e. power and ground inductance) and pin-to-pin coupling. Currently, IBIS
does not supply the data required to model pin-to-pin coupling, and not all SI
simulators support the inclusion of power and ground inductances/capacitance
networks. One approach is to include these effects by gardbanding the slow
and/or fast corners of the model and/or including these effects as a separate
line item in your timing budget, but (obviously) only you can determine if
that is 'accurate enough'.

>
> Best Regards,
>
> John Loo
> High Speed I/O PHY Products
> 408 435 6730
> john_loo@hp.com
>
>
Received on Mon Dec 27 16:14:16 1999