RE: Question regarding c_comp

Rich,

I think you are confusing him more than he needs to be.
Why do you say: "Ensure there is no appearance "C" in the
spice file. i.e. even remove all the metal capacitive terms
in the buffer"? Why should he remove the metal effects?

It sounds to me that you are either talking about generating
V-t curves for Quad which does not avoid the double counting
unless you reverse engineer a zero C V-t curve, or some
home made algorithms which may also require that.

To me it seems that Dave believed that I-V curves include
the capacitive effects, and therefore he was concerned about
double counting if he defined a non zero C_comp value. The
answer is that I-V curves do not include capacitive effects,
and C_comp should contain everything (transistors, metal, pad,
etc.) that you see when you look into the die at the pad.

Arpad Muranyi
Intel Corporation
==============================================================

-----Original Message-----
From: Mellitz, Richard [mailto:richard.mellitz@intel.com]
Sent: Friday, May 26, 2000 8:29 AM
To: ibis@vhdl.org
Subject: RE: Question regarding c_comp

It's not IV, it's VT. Extract a VT curve from a transistor level model for
just the silicon and no package. Ensure there is no appearance "C" in the
spice file. i.e. even remove all the metal capacitive terms in the buffer.
Now measure the intrinsic transistor capacitance C=I/(DV/DT). You're going
to love what you get. More on that later. In this packageless environment
this becomes C_comp. The VT curve was created with this capacitance. In a
behavioral model the C_comp needs to be there to excite the correct
reflections. However your simulator needs to understand that it may still be
in the circuit during drive time. If so, you may be double counting the
effect. You can compensate VT data for this effect too. This doesn't come of
most "canned" IBIS creation methods. You need to do this for ps level
correlation if your simulator does not de-embed this.

Speaking of ps scrubbing. At Arpad suggestion, we modeled C as a function of
V. The results went from tens of ps correlation to single ps correlation (in
a complex reflective network and suffice to say at high speeds). Anyone got
the time to write a BIRD for voltage controlled capacitance. FYI, We found a
we could fit most C data to a 4 order polynomial which is rather simple to
implement in spice.

BTW, We find a lamda/4 tline is better than a fixed delay tline for
correlation.
... Rich
-----Original Message-----
From: gedlund@us.ibm.com [mailto:gedlund@us.ibm.com]
Sent: Thursday, May 25, 2000 6:12 PM
To: Dave MacAdam
Cc: ibis@vhdl.org
Subject: Re: Question regarding c_comp

Dave,

C_comp represents all on-chip capacitance and needs to be set to the value
that correctly represents your FETs, ESD devices, and bond pad. The IV
curve part of the model data does not contain any capacitance information,
so you won't be double counting. If you are using s2ibis2, there is a
parameter in the control file that sets C_comp. You should use min, typ,
and max values. I think the best way to get the correct value is to ask
your SPICE program to print the appropriate device capacitance values and
tally them up. I always check C_comp by running behavioral and HSPICE
simulations with 1 ns open-ended transmission line on the output of the
driver. Let the wave slosh back and forth a few times and you'll see if
you got the capacitance right. (Thanks to Ross Pryor for this technique.)

There is a better list for user-related questions: ibis-users@vhdl.org.
The list you posted to tends more toward development-related topics. If
you want more information about making IBIS datasheets, check out the
cookbook under "free tools" or the accuracy handbook under "accuracy" on
the IBIS web site.

Good luck.

Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

Dave MacAdam <dsm@adc.idt.com> on 05/25/2000 10:02:37 AM

To: ibis@eda.org
cc:
Subject: Question regarding c_comp

I hope this is the correct address to post this type of question, if not

I apologize.

I'm confused about the usage of c_comp in my model. The pad that I'm
attempting to create a model for is being simulated using an extracted
netlist, which will include all pad capacitance (structure, esd etc.).
As I understand it, c_comp is the input cap of the input pin, and
therefore is contained in my netlist used to generate the I-V curves.

With this, should I put c_comp to zero else be 'double counting' this
capacitance when the user simulates using my model?

Thanks

Dave MacAdam

----------
Design Engineer
Integrated Device Technology, Inc.
Atlanta Design Center
Received on Mon May 29 07:49:10 2000