Arpad,
I don't think the IBIS specification should allow these test
loads. It is a mis-understanding of the purpose of these
test loads that results in these abuses. IBIS should lead
by explaining to the community the real purpose of test
loads and why it is important. Adding this capability
to the IBIS specification would definitely be in the wrong
direction.
Chris
-----Original Message-----
From: Muranyi, Arpad [mailto:arpad.muranyi@intel.com]
Sent: Thursday, May 10, 2001 4:44 PM
To: 'ibis@eda.org'
Subject: RE: IBIS BIRD71 - Timing Test Loads in [Model Spec] to Support
PC I & PCI-X
Stephen,
I have seen some specs (system bus on P4 platforms) which also
include transmission lines and series inductors, and other
elements (describing a package at the ends of the T-line) in
the reference or test load. Even though I strongly disagree
with such test loads, I feel we should address these too in
the IBIS spec. Do you think that this BIRD could be used to
extend the variety of load circuits?
Arpad
=================================================================
Date: Mon, 30 Apr 2001 15:19:51 -0700
From: Bob Ross <bob_ross@mentorg.com>
To: ibis@eda.org
CC: stephen.peters@intel.com
Subject: IBIS BIRD71 - Timing Test Loads in [Model Spec] to Support PCI &
PCI-X
To IBIS Committee:
Stephen Peters is submitting BIRD71 for consideration in IBIS Version 4.0.
Bob Ross
Mentor Graphics
****************************************************************************
**
****************************************************************************
**
BIRD ID#: 71
ISSUE TITLE: Timing Test Loads in [Model Spec] to Support PCI & PCI-X
REQUESTER: Stephen Peters, Intel Corp.
DATE SUBMITTED: April 30, 2001
DATE ACCEPTED BY IBIS OPEN FORUM: Pending
****************************************************************************
**
****************************************************************************
**
STATEMENT OF THE ISSUE:
The IBIS specification lacks a way to specify minimum and maximum values
for timing test load parameters. In addition, the current set of timing
test
load parameters (Cref, Rref) are applied to both edges of an output
waveform,
thus making them inadequate for describing the timing tests loads used by
the PCI-X bus specification.
****************************************************************************
**
STATEMENT OF THE RESOLVED SPECIFICATIONS:
The following additional subparameters are added to the [Model Spec]
keyword:
Cref, Rref, Vref_rising, Vref_falling, Cref_rising, Cref_falling,
Rref_rising,
Rref_falling, Vmeas_rising, Vmeas_falling.
Changes and additions to the [Model Spec] keyword are shown by the |* lines
|===========================================================================
==
| Keyword: [Model Spec]
| Required: No
| Sub-Params: Vinh, Vinl, Vinh+, Vinh-, Vinl+, Vinl-, S_overshoot_high,
| S_overshoot_low, D_overshoot_high, D_overshoot_low,
| D_overshoot_time, Pulse_high, Pulse_low, Pulse_time, Vmeas
|* Vref, Cref, Rref, Cref_rising, Cref_falling, Rref_rising,
|* Rref_falling, Vref_rising, Vref_falling, Vmeas_rising,
|* Vmeas_falling.
| Description: The [Model Spec] keyword defines four columns under which
| specification subparameters are defined.
|
| The following subparameters are defined:
| Vinh Input voltage threshold high
| Vinl Input voltage threshold low
| Vinh+ Hysteresis threshold high max Vt+
| Vinh- Hysteresis threshold high min Vt+
| Vinl+ Hysteresis threshold low max Vt-
| Vinl- Hysteresis threshold low min Vt-
| S_overshoot_high Static overshoot high voltage
| S_overshoot_low Static overshoot low voltage
| D_overshoot_high Dynamic overshoot high voltage
| D_overshoot_low Dynamic overshoot low voltage
| D_overshoot_time Dynamic overshoot time
| Pulse_high Pulse immunity high voltage
| Pulse_low Pulse immunity low voltage
| Pulse_time Pulse immunity time
|
| Vmeas Measurement voltage for timing measurements
| Vref Timing specification test load voltage
|* Cref Timing specification capacitive load
|* Rref Timing specification resistance load
|* Cref_rising Timing spec capacitive load for rising edges
|* Cref_falling Timing spec capacitive load for falling edges
|* Rref_rising Timing spec resistance load for rising edges
|* Rref_falling Timing spec resistance load for falling edges
|* Vref_rising Timing spec test load voltage for rising edges
|* Vref_falling Timing spec test load voltage for falling edges
|* Vmeas_rising Measurement voltage for rising edge timing
|* measurements
|* Vmeas_falling Measurement voltage for falling edge timing
|* measurements
|
| Usage Rules: [Model Spec] must follow all other subparameters under the
| [Model] keyword.
|
| For each subparameter contained in the first column, the
| remaining three hold its typical, minimum and maximum
values.
| The entries of typical, minimum and maximum be must be
placed
| on a single line and must be separated by at least one white
| space or tab character. All four columns are required under
| the [Model Spec] keyword. However, data is required only in
| the typical column. If minimum and/or maximum values are
not
| available, the reserved word "NA" must be used indicating
the
| typical value by default.
|
| The minimum and maximum values are used for specifications
| subparameter values that may track the min and max operation
| conditions of the [Model]. Usually it is related to the
| Voltage Range settings.
|
| Unless noted below, each subparameter does not require
having
| any other subparameter.
|
| Vinh, Vinl rules:
|
| The threshold subparameter lines provide additional min and
| max column values, if needed. The typ column values are
still
| required and would be expected to override the Vinh and Vinl
| subparameter values specified elsewhere. Note: the syntax
| rule that require inserting Vinh and Vinl under models
remains
| unchanged even if the values are defined under the [Model
| Spec] keyword.
|
| To mimic a hysteresis effect, the values of Vinh and Vinl
may
| be interchanged such that the Vinl value is larger than the
| Vinh value. However, simulators may process this
information
| differently or report an error.
|
| Vinh+, Vinh-, Vinl+, Vinl- rules:
|
| The four hysteresis subparmeters must all be defined before
| the hysteresis threshold rules become effective. Otherwise
| the standard threshold subparameters remain in effect. The
| hysteresis thresholds shall be at the Vinh+ and Vinh- values
| for a low-to-high transition, and at the Vinl+ and Vinl-
| values for a high-to-low transition.
|
| S_overshoot_high, S_overshoot_low rules:
|
| The static overshoot subparameters provide the voltage
values
| for which the model is no longer guaranteed to function
| correctly.
|
| D_overshoot_high, D_overshoot_low, D_overshoot_time rules:
|
| The dynamic overshoot values provide a time window during
| which the overshoot may exceed the static overshoot limits
| but be below the dynamic overshoot limits. D_overshoot_time
| is required for dynamic overshoot testing. In addition, if
| D_overshoot_high is specified, then S_overshoot_high is
| necessary for testing beyond the static limit. Similarly,
if
| D_overshoot_low is specified, then S_overshoot_low is
| necessary for testing beyond the static limit.
|
| Pulse_high, Pulse_low, Pulse_time rules:
|
| The pulse immunity values provide a time window during which
| a rising pulse may exceed the nearest threshold value but
| be below the pulse voltage value and still not cause the
| input to switch. Pulse_time is required for pulse immunity
| testing. A rising response is tested only if Pulse_high is
| specified. Similarly, a falling response is tested only if
| Pulse_low is specified. The rising response may exceed the
| Vinl value, but remain below the Pulse_high value.
| Similarly, the falling response may drop below the Vinh
value,
| but remain above the Pulse_low value. In either case the
| input is regarded as immune to switching if the responses
| are within these extended windows. If the hysteresis
| thresholds are defined, then the rising response shall use
| Vinh- as the reference voltage, and the falling response
shall
| use Vinl+ as the reference voltage.
|
|* Vmeas, Vref, Cref, Rref rules:
|*
|* The Vmeas, Vref, Cref and Rref values under the [Model Spec]
|* keyword override their respective values entered elsewhere.
|* Note that a Vmeas, Vref, Cref or Rref subparameters may not
be
|* used if its edge specific version (*_rising or *_falling) is
|* used.
|*
|* Cref_rising, Cref_falling, Rref_rising, Rref_falling,
|* Vref_rising, Vref_falling, Vmeas_rising, Vmeas_falling rules:
|*
|* Use these subparameters when specifying separate timing test
|* loads and voltages for rising and falling edges. If one
|* 'rising' or 'falling' subparameter is used, then the
|* corresponding 'rising' or 'falling' subparameter must be
|* present. The values listed in these subparameters override
any
|* corresponding Cref, Vref, Rref or Vmeas values entered
|* elsewhere.
|---------------------------------------------------------------------------
-- [Model Spec] | Subparameter typ min max | | Thresholds | Vinh 3.5 3.15 3.85 | 70% of Vcc Vinl 1.5 1.35 1.65 | 30% of Vcc | | Vinh 3.835 3.335 4.335 | Offset from Vcc | Vinl 3.525 3.025 4.025 | for PECL | | Hysteresis | Vinh+ 2.0 NA NA | Overrides the Vinh- 1.6 NA NA | thresholds Vinl+ 1.1 NA NA Vinl- 0.6 NA NA | All 4 are required | | Overshoot | S_overshoot_high 5.5 5.0 6.0 | Static overshoot S_overshoot_low -0.5 NA NA D_overshoot_high 6.0 5.5 6.5 | Dynamic overshoot D_overshoot_low -1.0 -1.0 -1.0 | requires | | D_overshoot_time D_overshoot_time 20n 20n 20n | & static overshoot | | Pulse Immunity | Pulse_high 3V NA NA | Pulse immunity Pulse_low 0 NA NA | requires Pulse_time 3n NA NA | Pulse_time | | Timing Thresholds | Vmeas 3.68 3.18 4.68 | A 5 volt PECL | | example | | Timing test load voltage reference example | Vref 1.25 1.15 1.35 | An SSTL-2 example | |* BEGIN ADDED EXAMPLE |* |* rising and falling timing test load example (values from PCI-X spec) |* Cref_falling 10p 10p 10p Cref_rising 10p 10p 10p Rref_rising 25 500 25 | typ value not specified Rref_falling 25 500 25 | typ value not specified Vref_rising 0 1.5 0 Vref_falling 3.3 1.5 3.6 Vmeas_rising 0.941 0.885 1.026 | vmeas = 0.285(vcc) Vmeas_falling 2.0295 1.845 2.214 | vmeas = 0.615(vcc) |* |* |* END ADDED EXAMPLE |=========================================================================== == **************************************************************************** ** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: BIRDxx is issued because of a long standing problem with specifying PCI compliant drivers. In PCI 2.2, minimum timing values are specified into a 0pF load, while maximum timing parameters are specified into a 50pF load. There was no way to specify this cleanly in IBIS. In addition, the PCI-X specification goes even further in specifying separate timing test loads for maximum rising and falling edges, and a single test load for the minimum case. In order to satisy the PCI-X spec all eight variations of Cref, Vref, Rref and Vmeas has to be included. Note that the PCI-X minimum test load is represented by it's Thevinen equivalent. **************************************************************************** ** ANY OTHER BACKGROUND INFORMATION: **************************************************************************** ** ---End of forwarded mail from Bob Ross <bob_ross@mentorg.com>Received on Thu May 10 17:41:33 2001
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