RE: IBIS BIRD71 - Timing Test Loads in [Model Spec] to Support PC I & PCI-X

Andrew,

Using the 25 ohm loads makes a lot of sense. Allowing a timing
test load for a rising edge that is different from the falling edge
may also be a good idea.

Testing a model with a real transmission line network is useful
to see if the IBIS model really captures the behavior of the model
under these conditions (with reflections coming back.) There is
an IBIS effort to define how to measure the accuracy of IBIS models
and that group is considering various transmission line loads.

However, the purpose of the timing test load is very specific and
important. The delay through the component, as specified by the IC
vendor, is the time from the logic switch of a receiver to the time
a driver reaches vmeas in response. That is the value the timing
analysis tools work with. The SI tools deliver the interconnect
delays which is the time that the receiver on the other end of
the interconnect switches minus the time-to-vmeas for the driver.
Thus the timing tools and the SI tools can work together.

More complex timing test loads would just make it more difficult
for timing tools and SI tools to cooperate. For example if the
reflection from the transmission line causes multiple crossings
of the Vmeas threshold, which one is the right one?

The IBIS accuracy work may add complex loads to the IBIS spec
for the purposes of validating models, but such complex loads
are not desirable for timing test loads.

Thanks,

Chris

-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
Sent: Friday, May 11, 2001 9:06 AM
To: 'ibis@eda.org'
Subject: RE: IBIS BIRD71 - Timing Test Loads in [Model Spec] to Support
PC I & PCI-X

> I don't think the IBIS specification should allow these test
> loads. It is a mis-understanding of the purpose of these
> test loads that results in these abuses. IBIS should lead
> by explaining to the community the real purpose of test
> loads and why it is important.
 
I haven't been paying full attention lately (too much stuff going on!), but
thought I'd chime in at this point.

In digital logic, most real loads look like unterminated transmission lines,
with some capacitance sprinkled in. The old lumped C or R-C load right on
the DUT pin is unrepresentative, and may be inadequate as a test load.

That is, in fact, why PCI 2.1 (not PCI-X, by the way) changed from the
ancient 50pF test load, to the two 25 ohm loads (for 3.3V PCI parts), each
representing a pair of 50 ohm traces in parallel; one case with the lines
previously in the low state, the other in the high state. This test load
emulates infinitely-long transmission lines, which is somewhat unrealistic
(but more representative than the lumped load).

Not only that, but there are times when a few nanoseconds of transmission
line, is a partciularly useful "test" load, such as when comparing
simulations of an IBIS model to a SPICE model. And it's a good, quick way
to visually see how a part behaves when its output "rattles around," quickly
exercising how the output transistors both source and sink current (as the
outputs go beyond the rails), as well as ESD clamping, reflection
coefficient, die capacitance, and package impedance. You can reveal a lot
about a part ... or its model ... in one quick test, which the old lumped
R-C model can never show.

Regards,
Andy

 
Received on Fri May 11 10:08:08 2001