Ccomp die is this static capacitance?

   What I would consider in modeling for Ccomp maybe differs from what is stated as being the Ibis spec for this. Through the transition region of switching, is my issue. In this portion where the signla is transitioning to another rail, the transistor FET AC model of C gs is what I want as a function of voltage. The idea here is that with the ringing of the package inductance I could have an issue depending on how I model the load, or even if I should put small compensation close to the output to get the best speed performance with the technology. Its hard to know if the Ccomp is underestimated in not giving this figure. I can see a low Ccomp when the active output ransisor is fully biased, but my rail margin makes this a bit moot. I could see two figures of characterisation of output capaictance to constrain the edsign at the chip end to the overall performance I would want as an integrator: one to measure the full on capacitnce to constrain to a good floor plan and another to characterise the transition AC performance to model better my source waveform and tLine and load. What more?

        Am I missing that there is something else in the package compensation to adress this?

Sounds like a circular argument between chip - tool - and board - think system view and make sure it considers the concern of the application and I would be completely happy that it s a real number.

Specs are no good if they are 1-not verfiable, 2 - not constraining the desing to adequate model and control electrical sytem design and PCBboard accomodations. Rest is easy.

Jeff Mills

Gecko Electronic Consulting of Contra Costa CA.

  ps take a nice bike ride, its very clarifying and weather has been great.