Subject: EIA IBIS Open Forum Meeting Minutes for 9/13/01
From: Guy de Burgh (gdeburgh@camarillo.innoveda.com)
Date: Wed Sep 19 2001 - 15:01:18 PDT
9/19/01
A number of members were lost from the ibis@eda.org list.
The problem has been corrected and they have been resubscribed.
The minutes are being resent to everyone on the list so that
those who did not get a copy the first time have a copy now.
I apologize if you have already received these minutes.
Guy de Burgh
Secretary.
DATE: 9/18/01
SUBJECT: September 13, 2001 EIA IBIS Summit Meeting Minutes
VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks) Roy Leventhal
Ansoft Corporation (Eric Bracken)
Apple Computer John Figueroa
Applied Simulation Technology [Raj Raghuram], Norio Matsui,
Fred Balistreri
Avanti (Chen Hongyu)
Cadence Design [Ian Dodd], Patrick Dos Santos, Heiko Dudek,
Lynne Green*, Lance Wang*
Cisco Systems Syed Huq, Lungfu Chen
Cypress Semiconductor (Rajesh Manapat)
EMC Corporation Brian Arsenault, Jinhua Chen
Fairchild Semiconductor Adam Tambone
Huawei Technologies Rachild Chen
IBM Michael Cohen, Greg Edlund, Wes Martin,
Yeon-Chang Hahm, Bill DeVey, Pravin Patel
Innoveda (& HyperLynx) Guy de Burgh, John Angulo, Cary Mandel,
Matthew Flora, Steve Kaufer
Intel Corporation Stephen Peters**, Arpad Muranyi*,
Dave Lorang, Michael Mirmak, Qinglun Chen,
Will Hobbs, Wei-hsing Huang
LSI Logic Larry Barnes
Mentor Graphics Bob Ross**, Tom Dagostino, Chris Reid,
Mike Donnelly, Hazem Hegazy, Tony Dunbar,
Griff Derryberry, Dan Lake, Sherif Hammad,
Mohammed Korany, Weston Beal, Chris Swaim*,
Ali Samii, Eric Ronger, Karine Loudet,
Daisaku Shiga, Kenji Kushima, Ian Dodd
Micron Technology Randy Wolff, Yong Phan
Mitsubishi Pat Hefferan
Molex Incorporated Gus Panella, Brian O'Malley
National Semiconductor Milt Schwartz
North East Systems Associates Edward Sayre*
Philips Semiconductor Zack Ciccone, Rob Mataheroe
Quantic EMC (Mike Ventham)
Signal Integrity Software Douglas Burns, Barry Katz, Walter Katz
Sigrity Raj Raghuram*, Winson Yu*
SiQual Scott McMorrow*, Rob Hinz, Bernard Voss,
Chris Brewster
Texas Instruments Thomas Fisher, Stephen Nolan, Ramzi Ammar,
Jean Claude Perrin, Moshiul Haque
Time Domain Analysis Systems Dima Smolyansky, Steve Corey
Tyco Electronics (Russell Moser)
Via Technologies (Weber Chuang)
Zuken (& Incases) John Berrie, Ralf Bruening
OTHER PARTICIPANTS IN 2001:
Actel Corporation Silvia Montoya
Acuson Kim Helliwell
AMCC Jeff Smith
ASIS Ltd David Wright
Brocade Communications Robert Badal
BMW Friedrich Hasinger
Cereva Networks Bob Haller*
Compaq [Peter LaFlamme], Ron Bellomio, Quang Dam,
Bill Ham
EADS Airbus Industry Claude Huet
(Aerospatiale)
EFM Ekkehard Miersch, Horle Raines
EIA Cecilia Fleming
Ericsson Radio Systems Anders Ekholm
FCI Sercu Stefaan
Foundary Networks Bertram Chan
Framatom Conectors Danny Morlion
Fraunhofer Institute Mariusz Faferko, Peter Kralicek
Reliability and
Integration
Fujitsu Ltd Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt
Hyundai Electronics Jongho Kang
Idaho State University Al Davis
Infineon Technologies Christian Sporrer
Intrinsix Corporation Steven Chin
KAW/USA Shinichi Maeda*
Motorola (Rick Kingen)
National Institute of Applied Etienne Sicard**
Science (INSA)
Nokia Tapani von Ravner, Mika Castren,
Janne Uusitalo
North Carolina State U. Paul Franzon**
Nortel Networks Calvin Trowell
Oak Technology Darmin Jin
Plexus Technology Group Joseph Socha
Siemens (& Automotive) AG Bernhard Unger, Helmut Katzier,
Katja Koller, Wolfram Meyer, Eckhard Lenski,
Gerald Bannert, Burkhard Muller,
Christian Marot, Manfred Maurer,
Amir Motamedi, Hans Pichlmaier
Sintecs Hans Klos
STMicroelectronics Peter Hirt, Fabrice Boissieres
Sun Adrian Udenze
Toshiba Corp. Hirokaza Kato, Yuichi Koga, Toshio Sudo
Xilinx Susan Wu
In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.
Upcoming Meetings: The bridge numbers for future IBIS teleconferences are
as follows:
Date Bridge Number Reservation # Passcode
October 5, 2001 1-888-316-5901 none 6159969
October 26, 2001 1-916-356-2663 3 0776283
All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.
Four people who attended by teleconference are designate by **.
NOTE: "AR" = Action Required.
-------------------------------- MINUTES -----------------------------------
IBIS SUMMIT MEETING LOGISTICS NOTE
The IBIS Summit meeting was held on Thursday, September 13, 2001 in the
Crowne Plaza Hotel located in Worcester, Massachusetts at the same time as
the PCB Conference East 2001. Because of the tragic attack on America on
September 11, 2001, the arrangements needed to be adjusted. Several people
were already attending the PCB Conference East, but others could not travel
to the site. After some consultation, we decided to hold the meeting as a
combined on-site/teleconference meeting. Intel provided the phone bridge.
A total of 14 people representing 11 organizations participated and 4 of
these people participated by telephone. Four of the presentations were
delivered by telephone and copies were available on-site.
INTRODUCTIONS AND BUSINESS
Stephen Peters welcomed the participants and thanked the co-sponsors Mentor
Graphics, North East Systems Associates, the IBIS Users Group and IBIS Open
Forum. Stephen also thanked Kathy Breda and North East Systems Associates
for the arrangements and for the last minute logistical adjustments. All
of the meeting presentation slides were available at the meeting and had
also been uploaded at the site:
http://www.eda.org/pub/ibis/summits/sep01/
Stephen stated that there were no business issues. Stephen asked for any
open topics. None were offered at that time, but at the end of the
meeting Arpad Muranyi gave a brief presentation:
Arpad Muranyi - Correlation Study for DDR Style Terminations with IBIS
Models
KEYNOTE REMARKS
Stephen Peters introduced Ed Sayre, Chair of the IBIS Users Group for some
keynote remarks.
After thanking Intel for the bridge, Ed expressed concern that the IBIS
specification was becoming too complex for the middle ground user and
becoming too hard to use. A tutorial is needed to understand the
specification, and a paper or presentation detailing the theoretical basis
behind IBIS behavioral modeling would be helpful. He also felt that while
the model developer needs to be concerned about the syntactical issues, the
user needs more graphical information content. In short, the basic concepts
need to be communicated better. Ed suggested that money and resources be set
aside for IBIS training.
The group commented and discussed Ed's remarks. Arpad Muranyi state that
complexity was added in Version 3.2 to deal with new technologies beyond the
original scope of IBIS. Bob Haller stated that the IBIS Cookbook (which
needs to be updated) has some graphical representations. Lynne Green commented
that users buy tools to do the work and engineers are more software literate,
and the participants agreed that most IBIS models are created by junior level
engineers. Raj Raghuram suggested that a university professor could write a
book or produce more information on IBIS. Bob Ross noted that EDA Vendors and
other commercial vendors often provide model training and model development
support and also stated that Arpad Muranyi has a four hour Real-Time video IBIS
tutorial that is available. Stephen Peters did acknowledge that the IBIS
Specification could be clearer.
PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions. These
notes capture some of the content and discussion. See the uploaded documents
for more detail.
FROM MODEL CREATOR TO MODEL USER
Bob Haller, Cereva Networks
Bob Haller started by showing that some public IBIS models still have a
large number of errors. Bob showed an AC termination simulation where IBIS
produced good results quickly. He also showed a simulation result where
the Spice model was appropriate.
Moving from model creator to model user, Bob now sees good and bad models.
He commented that he can identify and fix models and provide some vendor
feedback. Bob noted that given today's short design cycles one has to request
models early. Market forces are generally driving model quality, but he still
recommends verifying IBIS models in the lab.
Bob then went on to give examples of typical model problems. He noted that
the additional PCI loads will be handled in IBIS Version 4.0. However,
there are improvements and vendors are more responsive. Bob stated that work
is continuing on advances (Connector Specification, IBIS-X), and pointed to a
number of resources. These includes Syed Huq's DesignCon 2000 paper as well
as friends and colleagues.
Bob Ross commented that some good models are produced by EDA and commercial
vendors, and some of these vendor also help semiconductor vendors produce
models.
A PROPOSAL FOR s2ibis3
Paul Franzon and Michael Steer, North Carolina State University (NCSU)
Paul Franzon via teleconference gave some background showing strong
industrial connections and support for analog, RF and mixed mode research
based on federal funding. Paul is proud of the earlier NCSU s2ibis and
s2ibis2 contributions to IBIS and industry. A multi-university DARPA
project covers a number of advanced modeling and simulation abstractions:
Global Environment, Michael Steer, NCSU
Digital Behavioral Modeling and SSN Macromodeling, Paul Franzon, NCSU
Parasitic Extraction and Full Wave Modeling of Interconnect, Andreas
Cangellaris, U. of Illinois
Optoelectronic Modeling, Mark Neifeld, University of Arizona
Paul gave an overview of the other activities. Regarding his topic, he
planned a macromodeling tool for automatic accurate reduced-order SSN
modeling of on-chip digital structures from full circuit descriptions. Its
unique feature is a macromodel production tool similar to Spice2IBIS and
a complete SSN macromodel conversion tool.
Paul then covered point-by-point the s2ibis3 project requirements that were
issued by the IBIS sub-committee. Some notable points include:
C++ based, JAVA for graphics
Flex and Bison and portability through GNU and Cygwin in MS Windows
A separate IBIS parser may be developed
Improved algorithms and configuration options.
Improved Spice controls for improved convergence (e.g., Vdd ramping,
more .options, fixing some clamping problems, data point and time,
voltage step options, etc.)
In addition, the goals are to support:
GNU public license
Class structures to support digital and analog macromodeling with IBIS
as a subset
Be applicable for board level modeling and modeling of segments of mixed
signal chips
The research agenda includes support of IBIS-X with SSN macromodeling, 3-D
models, and testing and validating against Spice and measurement. Paul
intends to have industrial collaborators. This 3-year DARPA effort will
produce a spice2ibis3 and have strong industrial collaboration.
Several questions and suggestions were discussed during the presentation.
Ed Sayre and Lynne Green commented that the s2ibis3 utility should handle
differential models and models with strong feedback (such as those having
gate modulation). Numerical stability presents a challenge, and there was
a long discussion regarding the utility of models and simulators supporting
VDD ramping. Several people stated that they would investigate providing
some industrial support.
PROGRESS AND UPDATE ON THE CONNECTOR SPECIFICATION
Stephen Peters, Intel Corporation
Because of a conflicting meeting, Stephen Peters' two presentations
were moved up to this position in the meeting.
Stephen, via teleconference, stated that the IBIS Connector header and
about three-fourths of the technical description have been reviewed.
The Working Group plans to add the conductance matrix (G Matrix) for
losses and also frequency dependent simulations. Both the LRGC and
S-parameter formats are being considered. We expect a specification
completion by the end of January 2002 if there are no unexpected
technical issues.
Stephen gave some more detail on changes including even_mode, odd_mode,
and quiescent model types and Fork and Endfork under a [Path Description]
keyword. Electrical matrix "row" order can be random, so a pin number
to matrix map has been added.
Stephen and others then discussed the advantages of using
S-parameters versus RLGC matrices. S-parameters are more natural for
frequency domain simulations while RLGC are more natural and familiar to
engineers for time domain simulations. Ed asked if the inductance
matrix was for partial or loop inductances. Bob Ross indicated that
for full matrix the inductance is partial, however, there was some
discussion on whether loop inductances are appropriate for single
line models. After much discussion Stephen agreed to make sure that
the connector specification fully documents partial vs. loop inductances
and when each are used.
PROGRESS AND ISSUES IN IBIS-X
Stephen Peters, Intel Corporation
Stephen Peters stated that a simpler path into IBIS is being pursued.
Shortly after IBIS Version 4.0 is approved, the Working Group intends to
issue a BIRD to add the [Define 'class name'] concept. The work is now
focusing on the macro-language reference manual (IBIS-ML). This is being
reviewed and should be available in January 2002.
Stephen listed some technical milestones that have been met or are being
tracked. Then Stephen described the [Define "class name"] keyword. He
showed the syntax. It can be used in the IBIS file itself. Defines can
be collected in a library file. Once an object is defined, it can be
customized in the IBIS file.
Ed Sayre asked about backward compatibility with IBIS Version 3.2, and
Stephen said that IBIS Version 3.2 (and 4.0) will be supported by being
defined in the macro language.
MODELING THE RADIATED EMISSION OF MICRO-CONTROLLERS
Christian Marot, Siemens, Andre Peyre Lavigne, Motorola, Claud Huet, Eads
Airbus, Etienne Sicard, National Institute of Applied Science (INSA)
After lunch, Etienne Sicard, via teleconference, introduced the need for EMC
modeling of ICs. The industry is working with 0.12u, 6 metal technology
with up to 200,000,000 devices and CPU frequencies of 1 GHz. The dI/dt
switching speeds have become faster causing increased EMC problems. Etienne
showed identical devices from different vendors. One device designed without
considering radiation showed to be out of compliance by 20 to 40 dB compared
to other chip. Currently EMC problems are found after the fact and
require costly design iterations to correct.
The IERSET (a European research institution for research in transportation)
EMC project for ICs is co-sponsored by EADS Airbus, Siemens Automotive,
Motorola, Alcatel, INSA, and IERSET. The objectives are to define and
validate a model for PCB CAD tools to guarantee the EMC of electronic
systems. Its focus is on a model from 1 MHz to 1 GHz for conducted and
radiated emission. The French standards organization UTE has issued a
draft Integrated Circuit Electromagnetic compatibility Model (ICEM) and
forwarded it to IEC as a Committee Draft for Voting 62014-3. An ICEM
Cookbook Version 1c is available. ICEM presentations and papers are
planned at conferences, at company sites and at IBIS Summit meetings.
Etienne described the core emission model and its basic parameters Cd and
core noise generator Ib and advanced parameters for secondary resonance
Rvdd, Lvdd, Rvss, Lvss and Cb. He gave typical values and showed some
good measurement and simulation comparisons. In response to a question
by Raj Raghuram, Etienne clarified that the measurements and simulations
were for near field emissions. Scott McMorrow and others commented on the
resonance terminology since the since all resonances including the
"primary" resonance were many multiples above the 8 MHz fundamental clock
frequency. In response to Lynne Green's question some typical values of
all parameters were given (Cd - 300 pF to 20 nF, Cb - 1 nF, Lvdd and Lvss -
15 nH).
The equivalent current generator was extracted through Verilog gate level
simulation and simple statistical considerations. Spice and interpolated
transistor level methods had either size or number of device limitations.
The core emission model can be extended with an IBIS I/O model. An I/O
buffer is added along with a Cio decoupling capacitor and a substrate
resistance Zsub (typically 1 to 10 ohms). Etienne showed good simulation
predictions with TEM cell measurements up to 300 MHz with the core emission
model alone, and improved correlation up to 800 MHz when the I/O model was
added.
Etienne stressed that this is a relatively simple model that can be used for
predicting parasitic emission of complex chips. Bob Ross added that a link
to Etienne's work that includes several presentations and draft documents
exists under:
http://intrage.insa-tlse.fr/~etienne/Emc/index.html
POWER/GND SIMULATION USING IBIS MODELS AND PIN MAPPING ISSUES
Raj Raghuram, Sigrity, Inc.
In introducing the subject Raj Raghuram stated that analysis based on ideal
planes are no longer sufficient. Routing of traces through multiple layers
and with vias is now common. Advanced signal and power integrity now
combines the circuit along with trace transmission lines the pin RLC and
non-ideal ground and power plane simulation. This can take care of power
ground noise (SSN or Delta-I or ground bounce), effects of vias and return
path discontinuity, effects of decoupling capacitors, and edge radiation
from boards due to SSN.
The approach he takes is to do combined circuit/transmission line/power/
ground simulation with IBIS models in the time domain (in contrast to a
separate frequency domain power/ground analysis). He does need the [Pin
Mapping] keyword for the IBIS models. Raj showed some topologies and some
results. Full analysis distorts the signal, but well-placed decoupling
capacitors can produce a nearly ideal response since return path and
other discontinuities are bypassed. Raj provided plots illustrating the
improvement provided by decoupling capacitors.
Raj also illustrated some several types of devices with unique pin mapping
requirements. These included separating different supplies and possible
different clamp references from the buffer, core and I/O parts of the IC,
and separating analog and digital ground pins.
Raj stressed that [Pin Mapping] is essential and is a zeroth order effect
in simulation that includes more accurate ground and power effects.
Lynne Green asked if the decoupling capacitors had parasitic elements. Raj
responded that they did not, but the RL information was available form the
manufacturers and easy to add.
IBIS-X PRIMITIVES AND EXAMPLE
Lynne Green, Cadence Design Systems
Lynne Green introduced IBIS Version 3.2 as having a fixed topology with
some flexibility regarding values and allowable IBIS setups.
She listed some usages of "model" in IBIS as a "circuit" model for a
predefined topology, a "component" model for pins and packages and a
"buffer" model for numbers, vectors, and data tables. IBIS-X retains the
last two usages, but introduces a "behavioral" model where the model maker
defines the topology.
Lynne then used some examples to show some of the IBIS-X capability. The
simple model under [Define Model] inherited an existing IBIS Version 3.2
buffer model as a "model_base", but added voltage and temperature dependent
capacitor and resistor elements. Another example showed how resistor and
capacitor tables could be specified. As second buffer had the same tables
with different data.
IBIS-X "behavioral" models add components that model effects (such as
vsource), has symbolic values such as C_comp, has tables and equations for
components, and can deal with other variables such as time and temperature.
Lynne showed some primitives (resistor, capacitor, inductor, voltage and
current sources, voltage controlled voltage and current sources, and
transmission lines. She illustrated variations of the resistor primitive.
The model maker provides the model behavior, the model data, and pin list.
The users may provide pin lists (such as for FPGAs) and model selector
information.
Much discussion occurred during the presentation. Ed Sayre and others did
feel that the syntax and terminology was confusing and did not relate to
what engineers already know and use. We should use words with a common
context. This should be raised as an issue for the Futures committee.
It was not clear whether the set of primitives does or should include
current and voltage controlled current sources. Engineers are already
familiar with the set of four controlled sources. Options regarding coupled
transmission line modeling were discussed. One suggestion was to have
local temperature controlled resistors modeling thermal hot spots. IBIS-X
will continue to support MKS units. There was some concern over how EDA
vendors would support IBIS-X.
Lynne concluded that IBIS-X should be regarded as an extension of IBIS.
CORRELATION STUDY FOR DDR STYLE TERMINATIONS WITH IBIS MODELS
(Unscheduled Presentation)
Arpad Muranyi, Intel Corporation
Arpad Muranyi investigated the accuracy of the recommended waveform loads
with respect to the DDR style terminations such as 50 ohms to Vdd/2.
He showed two sets of results:
(1) V_fixture = 0, 5 V and R_fixture = 50 ohms
(2) V_fixture = 2.5 V, R_fixture = 50 ohms
Arpad's concern was that the results for (1) did not overlay for the
DDR termination. Also the results for (2) overlayed for the DDR termination
(same as the load), but gave bad results for 50 ohms to ground and Vdd for
both the rising and falling edges. His results were based on the HSPICE
B-element.
Scott McMorrow suggested a larger load resistance such as 100 ohms for (1)
because the voltages of the existing waveforms did not overlap center
region. Bob Ross suggested exploring Vdd/2 and 2Vdd/3 voltages with 50 ohm
loads to center the four waveform loads.
Arpad plans to send the ibis model to EDA vendors to test in their own tools
since they may have different algorithms.
[Added note, the uploaded presentations show that Scott's and Bob's
suggestions did not produce improved results]
FINAL BUSINESS
Bob Ross reported that the next IBIS Summit Meeting is scheduled on January
28, 2002 at DesignCon2002 in Santa Clara, California. We are also working
on arrangements for an IBIS Summit Meeting on March 8, 2002 at Date 2002 in
Paris, France. The weekly IBIS Working Groups on the Connector Specification
and on IBIS-X will continue next week.
Ed Sayre offered space at NESA to those who needed working facilities while
waiting for their return trips.
NEXT MEETING:
The next teleconference meeting will be on Friday October 5, 2001
============================================================================
NOTES
IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
stephen.peters@intel.com
Senior Hardware Engineer, Intel Corporation
M/S JF4-215
2111 NE 25th Ave.
Hillsboro, OR 97124-5961
VICE CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
bob_ross@mentor.com
Modeling Engineer, Mentor Graphics
8005 S.W. Boeckman Road, Wilsonville, OR 97070
SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
gdeburgh@innoveda.com
Senior Manager, Innoveda
1369 Del Norte Rd.
Camarillo, CA 93010-8437
LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
roy_leventhal@3com.com
Senior Engineer, CommWorks Corp. (a wholly owned 3Com
subsidiary)
1800 W. Central Rd.
Mt. Prospect, IL 60056-2293
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
jangulo@innoveda.com
Development Engineer, Innoveda
14715 N.E. 95th Street, Suite 200
Redmond, WA 98052
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============================================================================
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