Subject: Re: Clock limitations on IBIS simulation.
From: Dan Aleksandrowicz (dan@galileo.co.il)
Date: Tue Jan 08 2002 - 06:10:11 PST
Hi Andy.
I have looked into the package model and it seems very complex
to a high pin count device, like above 700 pins. In such cases
even pin specific R/L/C data consumes a lot of time.
Is there a simpler method to properly represent the package ?
Danny
"Ingraham, Andrew" wrote:
>
> Many IBIS models have just the simple L-R-C package model representing a
> single line. No couplings. Faster edge rates (and therefore clock
> speeds) may require a better representation of package parasitics. For
> some devices it may make more of a difference than others.
>
> At 1GHz, and for most high pin count IC packages, I would consider the
> simple L-R-C model to be inadequate. You do get into some tool
> dependencies here, as well: does the tool treat it as a distributed
> model? Lumped PI-model? L-model? T-model? Lossy delay? Are any of
> these appropriate for your particular device?
>
> Regards,
> Andy
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