Re: Clock limitations on IBIS simulation.

Subject: Re: Clock limitations on IBIS simulation.
From: Scott McMorrow (scott@vasthorizons.com)
Date: Tue Jan 08 2002 - 08:26:58 PST

Dan,

the simple answer to your question is:

If the power/ground and return path simulations are significant to
the performance of the system, then IBIS simulation will not
provide the correct results.

For the DDR case, on many devices up to 72 SSTL-2 I/O cells
can switch simultaneously within a package. It is currently not
possible for any IBIS simulation to correctly assess the effects
of SSO and return path discontinuities.

We use SPICE simulation for all of our DDR channel work. And
have correlated our pseudo random bit pattern eye simulations to
lab measurements.

regards,

scott 

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

Dan Aleksandrowicz wrote:

> Hi guys.
>
> I know this question is as old as IBIS itself, but, it still rising
> again.
>
> At what clock speeds, and yes I mean DDR signals, is IBIS not
> accurate to a intolerable degree ?
>
> I know that the DC sweep analysis is clock independent, and
> that the wave form reflects the actual switching of the pad.
> Therefor, I believe the answer is more tool dependent.
>
> Is the above assumption is true ? And please I am not looking
> into tool compression. But, into the theoretical aspects of high
> speed analysis in 1G and beyond.
>
> Please comment - thanks.
>
>     Danny Aleksandrowicz

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