Subject: EIA IBIS Summit Meeting Minutes
From: gdeburgh@innoveda.com
Date: Thu Feb 07 2002 - 08:16:39 PST
DATE: 2/7/02
SUBJECT: January 28, 2002 EIA IBIS Summit Meeting Minutes
VOTING MEMBERS AND 2002 PARTICIPANTS LIST:
3Com (& CommWorks) Roy Leventhal
Ansoft Corporation (Eric Bracken)
Apple Computer Kim Helliwell*
Applied Simulation Technology Fred Balistreri*, Norio Matsui*
Avanti (Hailong Wang)
Cadence Design Lynne Green*
Cisco Systems Syed Huq*, Abdulrahmun Rafiq*, Zhiping Yang*
Cypress Semiconductor (Rajesh Manapat)
EMC Corporation (Brian Arsenault)
Fairchild Semiconductor Adam Tambone*
Huawei Technologies (Rachild Chen)
IBM Greg Edlund*, Pravin Patel
Innoveda John Angulo*, Guy de Burgh*
Intel Corporation Stephen Peters*, Arpad Muranyi*, Will Hobbs*,
Pete Block*
LSI Logic Larry Barnes
Mentor Graphics Bob Ross*, Ian Dodd*, Mike Donnelly*,
Matt Hogan*
Micron Technology (Randy Wolff)
Mitsubishi (Tom Cao)
Molex Incorporated Gus Panella*
Motorola Rick Kingen
National Semiconductor Milt Schwartz*
NEC Corporation (Akimoto Tetsuya)
North East Systems Associates (Edward Sayre)
Philips Semiconductor (D.C. Sessions)
Quantic EMC (Mike Ventham)
Siemens (& Automotive) AG Helmut Katzier*
Signal Integrity Software Barry Katz*, Walter Katz*, Robert Moles*,
Daniel Nilsson*, Kevin Fisher*, Steve Coe*,
Wiley Gillmor*, Douglas Burns*, Eric Brock*,
Sigrity Raj Raghuram*
SiQual Scott McMorrow*, Dave Macemon*, Rob Hinz*
Texas Instruments Thomas Fisher*, (Jean-Claude Perrin)
Time Domain Analysis Systems Steve Corey*, Dima Smolyansky*
Tyco Electronics (Tim Minnick)
Via Technologies (Weber Chuang)
Zuken (& Incases) (Michael Schraeder)
OTHER PARTICIPANTS IN 2002:
Actel Prabhu Mohan*
Apt Software Atul Agarwal*
Brocade Communications Robert Badal*
Compaq Shafier-ur-Rahman*
EIA (Cecilia Fleming)
Matsushita (Panasonic) Atsuji Ito*
National Institute of Applied Sebastian Calvet (& Motorola)*
Science (INSA)
Northrup (Litton) Robert Bremer*
Shindengen Elecric Mfg. Co. Tsuyoshi Horigome*
TDK Yoshikazu Fujishiro*
Xilinx Susan Wu*, J.L. de Long*
In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.
Upcoming Meetings: The bridge numbers for future IBIS teleconferences are
as follows:
Date Bridge Number Reservation # Passcode
February 22, 2002 1-916-356-2663 3 1911733
(International Dial-in the same)
All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.
NOTE: "AR" = Action Required.
-------------------------------- MINUTES -----------------------------------
INTRODUCTIONS AND MEETING QUORUM
The IBIS Summit Meeting was held in Santa Clara, California at the Santa
Clara Convention Center. About 49 people representing 27 organizations
attended.
The notes below capture some of the content and discussions. The meeting
presentations and other material will be uploaded at:
http://www.eda.org/pub/ibis/summits/jan02/
Stephen opened the meeting and thanked DesignCon for providing the meeting
room and the booth space as part of our Associate Sponsorship of DesignCon.
He thanked Milt Schwartz and National Semiconductor for providing the hot
lunch, copies of the presentations and other local arrangements. Stephen
thanked Applied Simulation Technology for bringing a backup LCD projector.
He also thanked Guy de Burgh and Innoveda for providing and setting up the
IBIS booth #706 and for managing the collection of IBIS member company logo
plaques for the background.
Stephen asked everyone in the room to introduce themselves. The group was
well represented by semiconductor vendors and model providers, EDA tool
vendors, and users of IBIS models.
Stephen mentioned that three IBIS related presentations by members attending
the meeting were scheduled on Wednesday, January 30, 2002 in the DesignCon
2002 program. Finally, Stephen thanked the presenters and participants for
attending.
PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions. These
notes capture some of the content and discussion. More detail is in the
uploaded documents.
THE BITTER-SWEET EXPERIENCES OF USING IBIS MODELS
Barry Katz and Daniel Nilsson (Signal Integrity Software)
Barry Katz gave a brief overview of his company's involvement with design
and modeling and then introduced Daniel Nilsson, an experienced signal
integrity engineer. Daniel discussed the high-speed design challenges that
require a large number of simulations. IBIS model processing is helpful for
waveform analysis, timing analysis and system verification and can be as
accurate as transistor level analysis. Good models require effort, and
Daniel showed reasonable correlation results.
However, he illustrated some effects currently not captured in IBIS models:
Frequency dependent delays
Delay variation as a function of slew-rate
Signal amplitude delay variations
Daniel then showed steps to design success using IBIS models and concluded
the following:
IBIS models allow a larger solution space analysis
IBIS models creation requires significant effort, validation and
correlation
IBIS models can be used for designing 600+ MHz interfaces
In the discussion that followed, Raj Raghuram asked about the delay issue
and others suggested having a set of models covering specific ranges of
frequencies.
A CRITIQUE OF IBIS MODELS AVAILABLE FOR DOWNLOAD ON THE WEB - PART 1
Jim Bell and Dan Grogan (SiQual)
Scott McMorrow, who actually gave this presentation, opened by stating that
he hoped this report would spur semiconductor vendors into fixing their
models. Scott noted that this was a two part study. The first part documents
and analyzes the most frequent warnings and errors as reported by the
ibischk3 utility. Part 2 of this study will involve discovering IBIS model
problems not caught by ibischk3. Scott hoped to use the information
gathered to develop tools that will identify and fix model problems. Scott
also noted that the study was looking only at the error messages, not at
underlying causes, and only models that could be rendered into an ASCII text
file were considered.
According to the data presented, 69% of the models downloaded from IBIS
websites contain at least one significant error or warning. These errors
were grouped into extraction errors, structural errors, non-monotonic
warnings and syntax error and warnings. Some error and warnings (such as
filename errors and use of the tab character) were classified as don't cares
because they did not effect the simulation data.
Of the remaining errors, most involved problems with I-V tables being
either non-monotonic or not going through zero. Scott showed how some of these
errors could be fixed, either by editing the curve or in some cases shifting
an I-V table to eliminate clamp leakage currents. Another common error,
extreme currents present in the clamp tables, could also be corrected by
intelligently editing the I-V table. Other errors, such as the I-V table
unable to drive through Vref or the I-V table not agreeing with the V-T table
endpoints were more difficult -- if not impossible -- for the user to fix.
In summary, 40% of the downloaded models contained serious errors that had
to be fixed before the model could be used.
IBIS ACCURACY AT IBM
Greg Edlund (IBM)
Greg Edlund outlined the flow IBM uses for producing IBIS models from
transistor models. Using their in-house ASX circuit simulator a model
engineer will first extract the IBIS data. This data is then used to
create a behavioral model in ASX, which is then correlated with the
original transistor level model and a figure of merit is obtained.
Greg also described the method they use to extract realistic Vinh and
Vinl parameters. This method involves looking at the receivers transfer
function and selecting the actual (DC) input points at which the receiver
switches, as opposed to simply using the standard 0.8V and 2.0V numbers.
A short discussion was had on the difference between DC Vinl/Vinh
parameters and the switching threshold under AC conditions.
Greg then recounted some of the common problems he has encountered as a
model consumer. These problems range from incorrect C_comp values, to
missing or incorrect Vinl/Vinh data, to problems with V-T table endpoints
not matching the I-V table. Greg again recommended users force model quality
by including IBIS models specifically in their purchase specifications.
Finally, Greg displayed three different waveforms obtained from simulations
using actual models, showing how some of these incorrect models behave.
JEITA EDA ACTIVITY AND PROPOSAL
Atsuji Ito (Panasonic)
Atsuji Ito gave an overview of the Japan Electronics and Information
Technology Industries Association (JEITA) and organization, formed by the
merger of EIAJ and JEIDA. Under JEITA exists ECALS, a pilot test project
for the creation and distribution of technical information on semiconductor
and electronic parts.
The activities of the group center around:
Standardizing a dictionary for catalog parts development
Standardizing data distribution
Promoting commercialization
Promoting business applications
Two URLs exist giving more information:
http://www.jeita.or.jp/english/index.htm
http://www.e-parts.org/
Ito-san described the EDA Working Group activity under ECALS. Both IBIS and
Spice model formats are acceptable, and the major application is digital
consumer electronics. This field includes personal computers, digital
network appliances, consumer electronics (such as audio visual equipment)
and mobile phone and game electronics.
Currently IBIS is used for signal integrity. In the future Ito-san is
interested in power integrity and EMC applications. He presented some
issues and showed some applications. He also showed how IBIS and Spice are
used together. The major issue with IBIS is data accuracy.
Ito-san proposes that the ECALS EDA Working Group work with the IBIS Open
Forum to standardize passive components.
TO BE MODEL OF CIRCUIT SIMULATION
Tsuyoshi Horigome (Shindengen Electric Mfg.)
Tsuyoshi Horigome advocated having a unified design environment for digital,
analog, and high frequency effects that used an EDA models. He showed
good correlation with measurement and simulations using Spice models. The
IBIS-X macro language could also be used. The big issue is getting good
models.
PROPOSAL OF STANDARDIZATION OF PASSIVE COMPONENT MODEL
Yoshikazu Fujishiro (TDK)
Yoshikazu Fujishiro focused on passive component modeling. He compared
Spice, S-parameter (Touchstone format) and possibly IBIS model formats for
a lossy inductor. They all look promising, but he wants to investigate
the best solution.
In the discussion that followed for these three presentations, Arpad Muranyi
clarified that what is needed are analog models working in an analog
and mixed signal environment. Bob Ross suggested that the groups could work
together.
LOSSY LINE CHARACTERIZATION AND MODELING FOR SPICE AND IBIS
Steve Corey (Time Domain Analysis Systems)
Steve Corey gave the group a tutorial on transmission line loss, its
physical bases, and some issues he has encountered when trying to model
this loss.
To begin, Steve showed some examples of loss in both the time and frequency
domain and explained why modeling loss matters. Ignoring loss can cause
design failures when data rates are to high or drivers are to weak.
Conversely, overestimating loss can result in an overly conservative design.
He also noted that while loss has been considered in analog (microwave and
RF) design, most methods are frequency domain based and not targeted towards
broadband digital signals and time domain modeling.
Steve outlined the two major frequency dependent loss mechanisms in
conductors and dielectrics (PCBs). For conductors, varying skin depth causes
frequency dependent resistance loss while magnetic flux internal to metal
traces results in frequency dependent inductance. For dielectrics, there
are frequency dependent conductance losses as well as free moving charges
that cause frequency dependent capacitance losses. Steve noted that
dielectric losses are starting to trump conductor losses.
Steve then went on to outline the two different TEM modeling approaches,
lumped and distributed. Distributed models can further be divided into
those based on parameters (i.e. equations) and those based on RLGC matrixes.
When modeling loss, Steve noted that a good model must not only be accurate,
but it must also be passive (cannot generate energy) and causal. Stability
of the algorithm is important -- unstable algorithms can cause otherwise
passive models to blow up. Steve also emphasized that causality means that
frequency dependent R & L values are not independent of one another.
Likewise values of G and C are related.
Finally, Steve described TDA's loss modeling approach. They start with two
approximate equations that include DC values for R and G as well as some
loss terms. These loss terms are extracted from a TDR measurement of a
trace. Once the loss terms have been quantified, a simulation of the trace
and waveform is run. Lumped, parameterized and RLGC type simulations were
run and the results were compared against the original TDR trace. All three
simulation methods show good agreement wth the original waveform.
ICM: UPDATE
Augusto (Gus) Panella (Molex)
Gus Panella presented an update on the IBIS Connector Specification (ICM)
proposal. In brief, the connector working group has streamlined the keyword
structure and updated the document with proper formatting. The
specification has also been updated to include several new types of single
line model (SLM) choices and the ability to describe connectors using
S-parameters. To that end Stephen Peters authored a formal specification
describing the Agilent Touchstone(R) format. This document will be
referenced by the connector specification.
Gus went on to discuss current technical and direction issues. In order to
address frequency dependent effects, the working group will update the
current matrix format to allow connectors to be described using multiple
sets of matrixes, each set being taken at a different frequency. Gus also
raised the possibility of including packaging and/or PCB type descriptions
to the current specification, thus turning it into a general "interconnect"
specification. Arpad Muranyi pointed out that if the ICM specification is
to cover packages and PCBs then the current path description keyword must
include a 'join' statement along with named nodes. Stephen Peters commented
that the ICM specification has already been several years in the making.
While he would like to see the matrix descriptions re-used for a package
description, he would not want to delay the current ICM specification.
The meeting then adjourned for a delicious lunch hosted by National
Semiconductor.
IBIS/XML - ONE STEP FURTHER
Atul Agarwal (Apt Software Avenues)
Atul Agarwal, author of the ibischk3 parser, stated that IBIS/XML is useful
in separating content from presentation, providing a more structured
representation, and supporting Web services. There are some format details
concerning presentation of IBIS data (such as number of characters in a
line) that have to be addressed, but XML does have the advantage of being
simple, standard, structured, and textual. However, XML documents can be
large and difficult to read without tools.
Using IBIS/XML a new breed of Web services can be supported. Atul
listed several components that make up these web services:
SOAP (remote invocation)
UDDI (trader, directory service)
WSDL (expression of service characteristics)
XLANG/XAML (transactional support for complex web transactions involving
multiple web services)
XKMS (XML Key Management Specification) - ongoing work by Microsoft and
Verisign to support authentication and registration
Atul showed a block diagram for processing an XML document and demonstrated
the flow. He showed sample syntaxes for an IBIS Pin model, for an XSL
transformation, and a presentation format for XML for a Pin. XML files can
be generated from IBIS files, and IBIS files can be generated from XML files.
Atul also showed a choice for XML for a GND Clamp that expressed the
contents as elements or attributes.
Atul recommends these steps:
Standardize IBIS XML tags
Standardize IBIS XML DTD/XSD
Standardize IBIS presentation of XML
Modify ibischk3 to generate XML
He listed a few issues and gave some useful links for XML, EDA XML and
uploaded information in the IBIS sites.
Lynne Green asked if there exists XML plotting activity to assist in
presentation. Atul said no, but that would be a useful project.
EMI PARAMETERS FOR IBIS
Guy de Burgh (Innoveda)
Guy de Burgh presented a follow on to his IBIS Summit presentation
given in June 2001. He noted that signal integrity is mostly concerned
with voltage and time whereas EMI is mostly concerned with current and
frequency. Guy introduced some more optional parameters that can be easily
obtained. First he described the radiation modes:
Differential Mode
Current-Driven Common Mode
Voltage-Driven Common Mode
He introduced the EMI mechanisms:
Differential Mode - Direct radiation from loops.
Current-Driven Common Mode - Signal return currents create noise
voltages across finite return planes that drive attached cables.
Voltage-Driven Common Mode - Signal voltages and noise voltages due to
crosstalk drive attached cables.
Power Bus - Digital switching creates power noise.
Heatsinks - Act as antennas driven by potential differences on the
Return plane.
Crosstalk - Coupling among nearby traces.
Immunity - ESD, Magnetic and Electric Field Susceptibility.
Guy showed a differential mode EMI equation from a net based on the
far field approximation. He also gave some references.
Guy gave some proposed EMI parameters that are in addition to the
ones he introduced previously:
Voltage Range - The expected signal swing.
Component Type - To indicate whether the component is a connector.
Domain - To define whether the component is analog, digital or both.
Family - Describes the logic family for defaults (UNDEF, TTL, CMOS, ECL).
Ferrite - Indicates that the model for the pin is a ferrite.
Guy illustrated the syntax using [Component EMI] (including the power
dissipation capacitance Cpd, [Pin EMI] and [Model EMI] possible keywords.
The next steps to raise interest are to provide details of why the
parameters are needed, describe how to measure or where to find the
parameters and then to submit a BIRD.
A number of questions were asked to clarify the meaning and usage of the
proposed parameters. In response to Stephen Peters, Guy commented that the
calculation was a summation at a point of net-by net calculations. Bob
Ross asked if the Family subparameter was really needed, especially if it
could be UNDEF. Stephen Peters pointed out that it may be better to
explicitly define what piece of data is being asked for, rather than ask for
a general device technology. Finally, it was also noted that the Voltage
Range subparameter could be determined by the existing I-V table
information. Guy will take these suggestions under consideration.
ADVANCES ON THE ICEM MODEL FOR EMISSION OF INTEGRATED CIRCUITS
Sebastien Calvet (INSA, Motorola Semiconductor), Christian Marot, (Siemens
Automotive), Andre Peyre Lavigne (Motorola), Claude Huet (EADS Airbus), and
Etienne Sicard (INSA Toulouse).
Sebastian Calvet introduced himself as nearing completion on his PhD studies
in this field. The presentation is similar to the one by Etienne Sicard
given at the September 13, 2001 IBIS Summit meeting describing the
Integrated Circuits Electromagnetic Model (ICEM).
Technology advances in speed and complexity have resulted in severe
EMI problem; voltages have been reduced, but the di/dt has increased.
Devices from different vendors can exhibit orders of magnitude differences
in parasitic emission and some may not be EMC compliant. EMC compliance is
becoming an increasing need, therefore design methodologies need to include
tools and IC models for EMC simulation.
Sebastien showed good good agreement between predicted and measured radiated
emissions when using IBIS and a proposed core model. He outlined the research
project and noted the supporters from co-author organizations. This project
is under the European Research Centre on Electronics for Transportation
(IERSET). The draft standard was issued by the French standards organization
in February 2001 and the ICEM Cookbook Version 1.c was issued in August
2001. The ICEM draft is now a Draft Technical Report 93/146/CDV.
Sebastien briefly described the model for core noise of ICs originating
from gate switching. The three modes of coupling are:
Conducted: Power lines and I/Os
Radiated: Direct
He showed the added parameters and showed briefly how to get the values.
The equivalent current generator Ib is derived form simulations,
measurements or estimations. Sebastien showed good correlation with
predictions through 300 MHz with emission measurement in a TEM cell. The
core model works well, and at high frequencies the I/O effects dominate.
Sebastien used the pending IBIS-ML macro language to illustrate the syntax
of the proposed additions. In the future he would like to extend the model
to frequencies beyond 1 GHz and research susceptibility.
Stephen Peters asked whether the current source was describe by a current
versus time table, and Sebastien responded yes. More discussion occurred
regarding positioning this proposal and Guy de Burgh's proposal. It appears
they are both useful and may have different strengths.
IBIS VERSION 4.0
Bob Ross (Mentor Graphics)
Bob Ross briefly reminded us of each of ten BIRDs that have been approved
for pending IBIS Version 4.0. They consist of BIRD62.6, BIRD64.4, BIRD65.2,
BIRD66 and BIRD71, BIRD67, BIRD68.1, BIRD70.5, BIRD72.3 and BIRD73.4. Seven
of these involve syntax keywords and subparameter additions, and the others
involve clarification or limit changes.
Bob outlined the proposed plan:
After review, the IBIS Open Forum vote on Version 4.0 to stabilize the
syntax.
The ibischk4 parser project is started and more changes are anticipated
through clarification BIRDs
The IBIS Open Forum reviews and votes on Version 4.1.
This is packages for a formal EIA letter ballot and 3 month review and
response.
If successful, this becomes ANSI/EIA-656-B.
Bob estimated that this process would take one year. However, the IBIS
Version 4.0 should be stabilized around the June 2002 Design Automation
Conference time frame.
MULTI-LINGUAL MODEL SUPPORT WITHIN IBIS
Bob Ross (Mentor Graphics)
Bob Ross listed a number of benefits of multi-lingual support within IBIS
that are currently not adequately covered by the existing IBIS format.
These include advances in modeling details such as differential buffers,
controlled buffers, SCSI drivers, etc, and also more a complex die
interconnect description. A bonus is that IBIS can interface better with
true digital analysis through some existing analog/mixed signal (AMS)
languages. Bob then illustrated a number of these features using a sample
of a complex die provided by Tom Dagostino that captures a number of real
modeling requests and needs.
Bob stated that the multi-lingual approach leverages off of existing
investments in IBIS, Spice, VHDL-AMS, Verilog-AMS, etc. It still uses IBIS
for pinout, package, information and specification data, but calls and
executes external files when needed. Seven EDA vendors including some
larger ones already offer multi-lingual products that use the above
languages and others. Other tools used in PCB design and analysis provide
another form of multi-lingual support by importing/exporting Spice code. So
such support is natural. The proposal will still recommend the existing
IBIS format as appropriate. The proposed extensions are limited to a few
new keywords and can provide a fast response to the existing industrial
needs. The new keywords are classified as:
[External Model] for models defined in other languages
[External Circuit] for die interconnect circuit extensions
[Node Declarations] and [External Call] for connecting everything together
Bob showed a reference model for an I/O buffer. The IBIS electrical
connections including power supply rails were shown. The buffer is
controlled by true IEEE standardized digital signal to be compatible with
other languages. These were designated as D_drive, D_enable, and D_receive.
This approach is already taken in Spice implementations of IBIS models using
a psuedo logic 0 V and 1 V input as the control signal and receiver state
threshold detection signals. The standardized "digital" signals would still
be 0, 1, plus X, Z and other IEEE approved signal, as appropriate.
The syntax for [External Model] and [External Circuit] was described in
general terms. Each external reference contains four elements: name,
language, where the file is and the name of the model in the file, and the
interface ports. For Spice subcircuits and other language formats requiring
analog interfaces for digital controls, some additional A_to_D and D_to_A
subparameters are provided to translate digital control signals to or from
analog voltage levels. These voltages (such as 0 to 3.3 V or 0 to 1.0 V)
would provide the drive signals for Spice subcircuits. Threshold voltage
levels would be transformed to digital states. Some of the analog and
digital signal names would be reserved to promote model interchangeability.
In general, any name is acceptable.
The [External Model] keyword would reside within the [Model] keyword
(retaining Model_name as the name) and would override all other keywords and
subparameters under the [Model] keyword that describe electrical operation.
The [Model Spec] keyword is the only one that is not overridden.
The connection of the model is completed using the [Node Declarations] and
[Circuit Call] keywords. The die side of the pins are considered nodes with
the names as the pin numbers. Additional internal nodes are declared as
needed. The connection is by mapping ports to nodes in a manner that is
conceptually similar to using calls to Spice subcircuits. However, this can
be extended to include digital circuit interconnections.
Bob listed a few advantages and also raised some issues related to this
proposal. To maximize model inter-operability and minimize supporting
unique implementations, the IBIS Committee should encourage and endorse the
open, public, accepted languages. For example, Berkeley Spice is the subset
supported by most vendor specific Spices, is vendor-independent, and is
particularly useful for interconnect descriptions. Furthermore, it supports
the public BSIM4 model. The VHDL-AMS and Verilog-AMS versions should be the
open, standardized versions from independent bodies versus vendor-specific
HDLs.
Because some of the interaction details have not yet been sorted out, the
proposal is still being drafted. It will be issued as a new BIRD7X in the
near future.
A few questions were asked, and then the discussion covering both the IBIS-X
activity and this pending proposal followed the next presentation. Walter
Katz commented that a multi-lingual approach was already being done by his
company. Walter also suggested that parameter passing (such as temperature)
be added. Scott McMorrow commented that much of his work was now being done
in Spice. Bob suggested that the multi-lingual approach needs to be
examined when the formal BIRD is issued to judge how it fits in. He
suggested that at least the proposal might help the IBIS-X effort by showing
some target implementations.
PROGRESS AND ISSUES IN IBIS-X
Stephen Peters (Intel)
Stephen Peters updated the group on recent IBIS-X and IBIS Macro Language
(IBIS-ML) activity. The IBIS-ML specification is now at revision 0.6 with
basic syntax, language rules and circuit elements now defined and documented.
Transmission line circuit elements have also been added. Stephen noted
that the IBIS-ML parser activity in on hold pending a developer to work on
it. He also outlined two current IBIS-ML issues. One was adding support
for the [Model Spec] type of keywords and a second was determining if
a 'driver' element was good enough for first release.
Stephen also offered a few comments on the multi-lingual proposal. While
favoring the approach, he pointed out that modeling an I/O buffer in SPICE
or a behavioral description language such as VHDL-AMS means that a buffer
would no longer be described using I-V and V-T tables. This is a change
from the current way of thinking of IBIS as a 'data sheet'.
OPEN DISCUSSION
Walter Katz and Arpad Muranyi asked if people wanted the multi-lingual
approach rather than wait for IBIS-X. A number of people favored moving
forward on the multi-lingual approach. Walter suggested, as a first step to
introducing multi-lingual support and it's keyword, modifying IBIS so that a
[Model] could reside in another text file separate from an .ibs file.
A number of other points were raised. Model_type and the 13 [Model Spec]
parameters are still needed and would still be supported. The community
really does not want a new macro-language. Ian Dodd commented that IBIS-X
was really a marriage of data tables and executables. Lynne Green asked
what it would take to get VHDL-AMS to support I-V tables directly. In
the ensuing discussion, it was noted that the VHDL standardization committee
is on a five year cycle revision cycle, so it may take a while
for table support to occur.
CONCLUDING ITEMS
Stephen Peters thanked the presenters for great presentations. He noted
that the next teleconference meeting is scheduled for Friday, February 22,
2002. The next IBIS Summit meeting will follow in Paris, France on Friday,
March 8. 2002. He expects it to have strong emphasis on EMC/EMI issues.
NEXT MEETING:
The next teleconference meeting will be on Friday, February 22, 2002 from
8:00 AM to 10:00 AM Pacific time.
============================================================================
NOTES
IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
stephen.peters@intel.com
Senior Hardware Engineer, Intel Corporation
M/S JF4-215
2111 NE 25th Ave.
Hillsboro, OR 97124-5961
VICE CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
bob_ross@mentor.com
Modeling Engineer, Mentor Graphics
8005 S.W. Boeckman Road, Wilsonville, OR 97070
SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
gdeburgh@innoveda.com
Senior Manager, Innoveda
1369 Del Norte Rd.
Camarillo, CA 93010-8437
LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
roy_leventhal@3com.com
Senior Engineer, CommWorks Corp. (a wholly owned 3Com
subsidiary)
1800 W. Central Rd.
Mt. Prospect, IL 60056-2293
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
jangulo@innoveda.com
Development Engineer, Innoveda
14715 N.E. 95th Street, Suite 200
Redmond, WA 98052
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(ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
or both. State your request.
ibis-info@eda.org
To obtain general information about IBIS, to ask specific questions
for individual response, and to inquire about joining the EIA-IBIS
Open Forum as a full Member.
ibis@eda.org
To send a message to the general IBIS Open Forum Reflector. This
is used mostly for IBIS Standardization business and future IBIS
technical enhancements. Job posting information is not permitted.
ibis-users@eda.org
To send a message to the IBIS Users' Group Reflector. This is
used mostly for IBIS clarification, current modeling issues, and
general user concerns. Job posting information is not permitted.
ibischk-bug@eda.org
To report ibischk2/3 parser bugs. The Bug Report Form Resides on
eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
bugs.
To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
/pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
/pub/ibis/bugs/s2iplt/bugsplt.txt respectively.
Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:
http://www.eigroup.org/ibis/ibis.htm
Check the pub/ibis directory on eda.org for more information on previous
discussions and results. You can get on via FTP anonymous.
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