Subject: [IBIS] BIRD75.1 - Multi-Lingual Model Support
From: Ross, Bob (bob_ross@mentorg.com)
Date: Fri May 03 2002 - 13:22:56 PDT
To IBIS Commitee:
BIRD75.1 is issued with some minor editorial choices including changing
Spice to SPICE. The registration choice recommended by the IBIS
Futures group is included in the main line, and the alternative is
in the ANALYSIS ... Section. Except for very minor spelling/English
corrections, changed lines are shown by |* lines.
Bob Ross
Mentor Graphics
******************************************************************************
******************************************************************************
BIRD ID#: 75.1
ISSUE TITLE: Multi-Lingual Model Support
REQUESTER: Bob Ross, Mentor Graphics
DATE SUBMITTED: March 29, 2002, May 3, 2002
DATE ACCEPTED BY IBIS OPEN FORUM: Pending
******************************************************************************
******************************************************************************
STATEMENT OF THE ISSUE:
A rapid solution is needed for complex buffer modeling beyond what IBIS
currently supports and for more complex die interconnect circuitry. The
IBIS specifications already has too many keywords to support additional
expansion. The process of developing a new specification is turning out
to be more time-consuming than anticipated.
******************************************************************************
STATEMENT OF THE RESOLVED SPECIFICATIONS:
Multi-lingual model support within IBIS can leverage publicly accepted and
standardized language implementations such as SPICE, VHDL-AMS, Verilog-AMS,
etc. to support extended buffer behavior and extended interconnect
descriptions. This proposal still uses much of IBIS directly for pinout,
package, specification and information content and proposes linking to
external code for an additional method to simulate electrical performance
and report parameters.
This is all covered in a new Section 6b. Originally the keywords were to
be blended in the mainline Specification, but there were enough changes
and interactions to justify a new Section 6b similar to the Add Submodel
Description section.
|=============================================================================
|=============================================================================
|
| Section 6b
|
| M U L T I - L I N G U A L M O D E L D E S C R I P T I O N
|
|=============================================================================
|=============================================================================
|
| Multi-lingual support within IBIS is provided within .ibs files to allow
| extended descriptions of buffers and internal die interconnect circuitry
| that currently can be described using other languages and formats. These
| languages include SPICE, VHDL-AMS and Verilog-AMS.
|
| The extensions use the existing .ibs file format. They consist of the
| following keywords:
|
| [External Model], [End External Model] - Extended model description
| [External Circuit], [End External Circuit] - Circuitry on the die
| [Node Declarations], [End Node Declarations] - Interconnect nodes
| [Circuit Call], [End Circuit Call] - Connection description
|
| EXTERNAL LANGUAGES:
|
| IBIS files containing external language references can reference any or all
| of the languages, even for the same [Component] or set of [Model] keywords
| that the [Component] references.
|
| The allowed languages are arguments for the Language subparameter:
|
| "SPICE" means SPICE 3, Version 3F5 developed by the University of California
| at Berkeley, California. Many vendor specific EDA tools are compatible with
| most or all of this version.
|
| "VHDL-AMS" means "IEEE Standard VHDL Analog and Mixed-Signal Extensions",
| approved 18 March 1999 by the IEEE-SA Standards Board and designated
| IEEE Std 1076.1-1999.
|
| "Verilog-AMS" means Analog and Mixed-Signal Extensions to Verilog-HDL as
| documented in the Verilog-AMS Language Reference, Version 2.0. This
| document is still being developed by Accellera (formerly Open Verilog
| International), an independent organization and author of the Verilog
| Hardware Description Language IEEE 1364-2001. In the future, "Verilog-AMS"
| will mean the officially approved standardized version of the work under
| development.
|
| In addition the "IEEE Standard Multivalue Logic System for VHDL Model
| Interoperability (Std_logic_1164)" designated IEEE Std 1164-1993 is required
| to promote common digital data types.
|
| Each of these formats have methods to pass local or global parameters such
| as temperature, scaling, initial conditions, values, etc. into the portion
| of code that is being simulated. This support will continue to be done in
| the externally referenced files, but not in the .ibs file.
|
| REFERENCE DIAGRAMS:
|
| The details of the keywords are described later. For reference, the
| external model descriptions apply to but are not limited to the following
| diagrams:
|
| D_enable ___
| |
| |\
| D_drive____| \_______A_signal
| | / |
| |/ /| |
| D_receive____/ |__|
| \ |
| \|
|
| By convention, digital electrical ports are denoted by D_* and analog
| electrical ports are denoted by A_*. These prefixes are not required. The
| port names are used to describe interconnections within the IBIS file. The
| terminal names in the actual external models might differ from the port name
| assignment.
|
| Another reference diagram shows additional ports for power and other
|* connections. Except for <another name> ports, the names below are on the
| reserved port name list discussed later and relate to existing IBIS
| conventions.
|
| +---------+
| D_enable---| |---A_puref
| ||\ |---A_pcref
| D_drive----|| >----+-----A_signal
| ||/ /| | |---A_gcref
| D_receive--| < |--+ |---A_pdref
| | \| |---A_gnd
| | |---A_extref
| +--+---+--+
| | |
| D_<another name> ---+ +------A_<another name>
|
| A diagram below shows I/O Buffers connected directly to the die pad
| interface side of the package model. The top buffer shows some power pin
| connections and the bottom buffer shows only the signal connection with
| actual power supply values documented internally as in existing IBIS models.
| Either of these buffers can be an existing IBIS model or an [External Model]
| referenced in another file.
|
| _________________
| Die Nodes |
| |
| +---------+ |
| | |---*|
| ||\ |---*|
| || >----+-----*|
| ||/ /| | |---*|
| | < |--+ |---*|
| | \| | |
| +---------+ |
| |
| |
| Internal |
| Supplies |
| +---------+ |
| | | |
| ||\ | |
| || >----+-----*|
| ||/ /| | | |
| | < |--+ | |
| | \| | |
| +---------+ |
| |
|
| The [External Circuit] keyword is used to describe paths that can connect
| some or all of a [Model] to the 'Die Nodes' as shown in the diagram below.
| The connections between [Model] and [External Circuit]s are always through
| nodes. 'Internal Nodes' are shown for some connections and need to be
| declared. The diagram shows 'Die Nodes' designated by corresponding pin
| numbers, and 'Internal Nodes' by alpha characters. This diagram is used to
| illustrate the new keywords discussed later.
|
| ___________________________________
| Internal Nodes Die Nodes |
| |
| +---------+ +----------+ |
| | A |--(a)--| External |---*| 10 Vcc
| ||\ |--(b)--| Circuit | |
| || >----+----(c)--| (e.g., |---*| 1 Buffer A
| ||/ /| | |--(d)--| Die | |
| | < |--+ |--(e)--| connect) |---*| 11 GND
| | \| | | | |
| +---------+ | BUS | |
| | | |
| +---------+ | | |
| | B |--(f)--| BUS_SPI | |
| ||\ |--(g)--| | |
| || >----+----(h)--| BUS_VHD |---*| 2 Buffer B
| ||/ /| | |--(i)--| | |
| | < |--+ |--(j)--| BUS_V | |
| | \| | | | |
| +----+----+ +----------+ |
| | |
| | Analog Buffer Control |
| +---------------------------*| 3 Control Resistor
| | or Voltage
|
| Buffers A and B are shown connected through BUS to the numbered die
| connections. Buffer B has an additional buffer strength connection set
| by an external resistor or voltage. Internal nodes shown as characters
| (a)-(j) in the diagram must have names that are different from die node
| names.
|
| The [Node Declarations] and [Circuit Call] keywords presented later connect
| ports of [External Model]s or [External Circuit]s to internal or die nodes.
| An [External Circuit] or portions of it can also be connected to another
| [External Circuit] through internal nodes.
|
| KEYWORD DEFINITIONS:
|
| The [External Model] keyword is positioned within a [Model] keyword for
| which the [External Model] is used.
|
|=============================================================================
| Keyword: [External Model], [End External Model]
| Required: No
| Description: Used to reference an external file for a more detailed buffer
| description.
| Sub-Params: Language, Corner, Ports, D_to_A, A_to_D
| Usage Rules: The keyword [External Model] must appear only once for each
| [Model] keyword. It is not permitted under the [Submodel]
| keyword.
|
| Language:
| Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS". The Language
| subparameter is required and can appear only once.
|
| Corner:
| Three entries follow the Corner subparameter on each line:
|
| corner_name file_name circuit_name
|
| The corner_name entry is "Typ", "Min", or "Max". The
| file_name entry points to the referenced file in the same
| directory as the .ibs file.
|
| The circuit_name entry provides the name of the circuit within
| the referenced file to be executed by the EDA tool. For SPICE
| files, this is normally a ".subckt" name. For VHDL-AMS files,
| this is normally an "entity", "architecture" name pair with
| the architecture name enclosed in parenthesis. For
| Verilog-AMS files, this is normally a "module" name.
|
| Up to three Corner lines are permitted. A "Typ" line is
| required and shall be used for any missing corner ("Min" or
| "Max").
|
| No character limits, case-sensitivity limits or extension
| conventions are required nor enforced for file_name and
| circuit_name entries. However, the total number of characters
| in each Corner line must comply with the Section 3 limits.
| Furthermore, it is recommended that lower-case file_name
| entries be used to avoid possible conflicts with file naming
| naming conventions in different operating systems. It is
| also recommended not to rely on case-sensitive differences
| between otherwise identical file_name entries or circuit_name
|* entries. Several target code formats do not support
| case-sensitive distinctions.
|
| Ports:
| Gives port names to the terminals as "ports" that are used to
| connect the external model. The port assignment is by
| position, and the port names do not have to match exactly the
| terminal names of the external model. A list of pre-defined
| port names is presented later. The list of port names can be
| presented over several lines by using the Ports subparameter
| for each line.
|
| D_to_A, A_to_D:
| Defines all digital to analog and analog to digital electrical
| interface adapters needed to interface with the digital
| interface of reference models. While the IBIS format assumes
| that the EDA tool itself describes and controls how and when
| the IBIS model transitions occur, some external code needs
| explicit control circuitry to be executed. For example,
| logical states control implied in IBIS requires actual input
| voltage stimuli (such as a voltage ramp input) to simulate in
| SPICE.
|
| The D_to_A subparameter is used to convert a digital stimulus
|* ('0' and '1') into an analog voltage ramp, if needed. The
|* D_to_A subparameter is followed by the following entries:
|
| d_port port1 port2 vlow vhigh trise tfall
|
| The d_port entry is the digital port name. This entry is used
| for reserved port names: D_drive, D_enable and D_switch. The
| port1 and port2 entries name the analog ports across which
| voltages are specified. These ports must have been named by
| the Ports subparameter. The vlow and vhigh entries are 0
| percent and 100 percent voltages where the vhigh value is
| greater than the vlow value. The trise and tfall entries must
| be positive and give the input ramp rise and fall times
| defined between 0 and 100 percent.
|
| The stimulus is applied across port1 and port2. Normally
| port1 is the input and port2 is the reference. However, for
| an opposite polarity stimulus, port1 can be connected to a
| positive voltage reference and port2 can serve as the input.
|
| The A_to_D subparameter is used to generate a digital state
| ('0', '1', or 'X') based on detecting analog voltages. The
| A_to_D subparameter is followed by the following entries:
|
| d_port port1 port2 vlow vhigh
|
| The d_port refers to the digital port name and is used for the
| reserved port name: A_receive. The voltage measurements are
| taken from the port1 entry with respect to the port2 entry.
| These ports must have been named by the Ports subparameter.
| The vlow and vhigh entries are the low and high threshold
| voltage values. The reported digital state will be '0' if
| the measured voltage is lower than the vlow value, '1' if
| above the vhigh value, and 'X' otherwise.
|
| For differential buffers discussed later, the A_to_D
| subparameter is still used. For a true differential external
| model, port1 and port2 are the two differential ports, often
| with reserved names A_signal_p and A_signal_n. The [Diff Pin]
| subparameter vdiff would be mapped as follows: -vdiff value
| for vlow, and the +vdiff value for vhigh. The reported logic
| states produced by the A_to_D conversion follow the same rules
| as for single-ended buffers. The [Diff Pin] keyword is
| permitted, but ignored, since the A_to_D entries are used.
|
| For differential buffers composed of individual, single-ended
| buffers, but described by the [Diff Pin] keyword, the
| A_to_D connection is done implicitly. It requires the usage
| of the reserved signal name A_signal for each I/O port of the
| [External Model]. The port1 connection is the A_signal port
| of the Non-inverting model, and the port2 connection is the
| A_signal port of the Inverting model. If an adapter needs to
| be configured, its vhigh takes the +vdiff value, and vlow
| takes the -vdiff value. This is illustrated later and also
| applies if [External Model] is not used.
|
| Other Notes: The [External Model] keyword overrides all other keywords
| and subparameters that describe electrical behavior. This
| includes [Add Submodel], [Driver Schedule] and the C_comp
| subparameter and all other keywords under [Model] except
| [Model Spec]. [External Model] is not permitted under the
| [Submodel] keyword. Additional permitted keywords for the
| next release of IBIS are listed in the Keyword Interaction
| Limits section below.
|
| If other keywords exist under [Model], they must form a
|* complete set to comply with IBIS syntax rules as if the
|* [External Model] were not present. The other keywords can be
|* used for documentation or as a default mode of operation
|* should the [External Model] keyword and its suparameters be
|* be deleted or not supported.
|-----------------------------------------------------------------------------
| SPICE Example:
|
[Model] B
Model_type I/O
|
| ... Other model subparameters including C_comp.
|
[External Model]
Language SPICE
| Corner corner_name file_name circuit_name (.subckt name)
Corner Typ buffer_typ.spi buffer_io_typ
Corner Min buffer_min.spi buffer_io_min
Corner Max buffer_max.spi buffer_io_max
| Ports List of port names (in same order as in SPICE)
Ports A_signal int_in int_en int_out A_control
Ports A_puref A_pdref A_pcref A_gcref
| D_to_A d_port port1 port2 vlow vhigh trise tfall
D_to_A D_drive int_in A_gcref 0.0 3.3 0.5n 0.3n
D_to_A D_enable int_en A_gcref 0.0 3.3 0.5n 0.3n
| A_to_D d_port port1 port2 vlow vhigh
A_to_D D_receive int_out A_gcref 0.8 2.0
|
[End External Model]
|
| VHDL_AMS Example:
|
[External Model]
Language VHDL-AMS
| Corner corner_name file_name circuit_name entity(architecture)
Corner Typ buffer_typ.vhd buffer(buffer_io_typ)
Corner Min buffer_min.vhd buffer(buffer_io_min)
Corner Max buffer_max.vhd buffer(buffer_io_max)
| Ports List of port names (in same order as in VHDL-AMS)
Ports A_signal A_puref A_pdref A_pcref A_gcref A_control
Ports D_drive D_enable D_receive
|
[End External Model]
|
| Verilog_AMS Example:
|
[External Model]
Language Verilog-AMS
| Corner corner_name file_name circuit_name (module)
Corner Typ buffer_typ.v buffer_io_typ
Corner Min buffer_min.v buffer_io_min
Corner Max buffer_max.v buffer_io_max
| Ports List of port names (in same order as in Verilog-AMS)
Ports A_signal A_puref A_pdref A_pcref A_gcref A_control
Ports D_drive D_enable D_receive
|
[End External Model]
|
|=============================================================================
|
| The [External Circuit] keyword and subparameters can be positioned as a
| group before or after any [Component] keyword group. This rule is similar
| to how the [Model] keyword can be positioned within a file.
|
|=============================================================================
| Keyword: [External Circuit], [End External Circuit]
| Required: No
| Description: Used to reference an external code file for more detailed
| die interconnect description.
| Sub-Params: Language, Corner, Ports
| Usage Rules: Each [External Circuit] keyword is followed by a unique name
| that differs from any other name used for [Model] or
| [Submodel]. The [External Circuit] name is referred to as
| 'Ext_name', and a [Model] name is referred to as 'Model_name'
|
| The keyword [External Circuit] can appear multiple times. It
| is not scoped by any other keyword.
|
| Each [External Circuit] is referenced in a unique manner by
| [Circuit Call] keywords that are part of the [Component]
| keyword. The [Model] keyword is referenced in a similar
| manner.
|
| Language:
| Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS". The Language
| subparameter is required and can appear only once.
|
| Corner:
| Three entries follow the Corner subparameter on each line:
|
| corner_name, file_name and circuit_name
|
| The corner_name entry is "Typ", "Min", or "Max". The
| file_name entry points to the referenced file in the same
| directory as the .ibs file.
|
| The circuit_name entry provides the name of the circuit within
| the referenced file to be executed by the EDA tool. For SPICE
| files, this is normally a ".subckt" name. For VHDL-AMS files,
| this is normally an "entity", "architecture" name pair with
| the architecture name enclosed in parenthesis. For
| Verilog-AMS files, this is normally a "module" name.
|
| Up to three Corner lines are permitted. A "Typ" line is
| required and shall be used for any missing corner ("Min" or
| "Max").
|
| No character limits, case-sensitivity limits or extension
| conventions are required nor enforced for file_name and
| circuit_name entries. However, the total number of characters
| in each Corner line must comply with the Section 3 limits.
| Furthermore, it is recommended that lower-case file_name
| entries be used to avoid possible conflicts with file naming
| naming conventions in different operating systems. It is
| also recommended not to rely on only case-sensitive
| differences between otherwise identical file_name entries or
|* circuit_name entries. Several target code formats do not
|* support case-sensitive distinctions.
|
| Ports:
| Gives port names to the terminals as "ports" that are used to
| connect the external circuit. The port assignment is by
| position, and the port names do not have to match exactly the
| terminal names of the external circuit. The list of port
| names can be presented over several lines by using the Ports
| subparameter for each line.
|
| Other Notes: Certain other required and optional keywords under
|* [Component] can conflict with [External Circuit]. For
|* example, the optional [Pin Mapping] keyword might provide
|* different information. Other conflicting keywords are noted
|* in the Keyword Interaction Limits section below.
|-----------------------------------------------------------------------------
| SPICE Example:
|
[External Circuit] BUS_SPI
Language SPICE
| Corner corner_name file_name circuit_name (.subckt name)
Corner Typ bus_typ.spi Bus_typ
Corner Min bus_min.spi Bus_min
Corner Max bus_max.spi Bus_max
|
| Ports are in same order as defined in SPICE
Ports vcc gnd io1 io2
Ports int_ioa vcca1 vcca2 vssa1 vssa2
Ports int_iob vccb1 vccb2 vssb1 vssb2
|
[End External Circuit]
|
| VHDL_AMS Example:
|
[External Circuit] BUS_VHD
Language VHDL-AMS
| Corner corner_name file_name circuit_name entity(architecture)
Corner Typ bus.vhd Bus(Bus_typ)
Corner Min bus.vhd Bus(Bus_min)
Corner Max bus.vhd Bus(Bus_max)
|
| Ports are in the same order as defined in VHDL-AMS
Ports vcc gnd io1 io2
Ports int_ioa vcca1 vcca2 vssa1 vssa2
Ports int_iob vccb1 vccb2 vssb1 vssb2
|
| Verilog_AMS Example:
|
[External Circuit] BUS_V
Language Verilog-AMS
| Corner corner_name file_name circuit_name (module)
Corner Typ bus.v Bus_typ
Corner Min bus.v Bus_min
Corner Max bus.v Bus_max
|
| Ports are in the same order as defined in Verilog-AMS
Ports vcc gnd io1 io2
Ports int_ioa vcca1 vcca2 vssa1 vssa2
Ports int_iob vccb1 vccb2 vssb1 vssb2
|
[End External Circuit]
|
|=============================================================================
|
The following keywords are scoped by each [Component] keyword. They apply
for the specific set of pin numbers and internal nodes for only that
[Component].
|
|=============================================================================
| Keyword: [Node Declarations], [End Node Declarations]
| Required: No
| Description: Provides a list of internal nodes for interconnections.
| Sub-Params:
| Usage Rules: Each [Node Declarations] keyword contains a list of internal
| die nodes. Each node is separated by white space. The list
| may be positioned over several lines and is terminated by the
| [End Node Declarations] keyword.
|
| Only one [Node Declarations] keyword is permitted for each
| [Component] keyword. The [Node Declarations] keyword is
| part of the [Component] keyword, so all internal node
| references apply only to that [Component].
|
| If used, the [Node Declarations] keyword must appear before
| any [Circuit Call] keyword under the [Component] keyword.
|
| The internal node names within [Node Declarations] must be
| different from the pin_number names used in the [Pin] keyword.
| These pin_number names also serve as the terminals of the die
| and are also referred to as die nodes.
|-----------------------------------------------------------------------------
[Node Declarations] | Must appear before any [Circuit Call] keyword
|
a b c d e
f g h i j | Internal nodes, one or more lines permitted
|
[End Node Declarations]
|
|=============================================================================
| Keyword: [Circuit Call], [End Circuit Call]
| Required: No
| Description: Defines connections between the terminals of external circuits
| or models designated as ports and the declared internal nodes
| or the die nodes at the die interface.
| Sub-Params: Port_map, Cell_port, Diff_cell_port, Series_cell_port
| Usage Rules: Each [Circuit Call] is followed by a Model_name or Ext_name
| that references the IBIS [Model] keyword Model_name or the
| [External Circuit] Ext_name.
|
| The keyword [Circuit Call] can appear multiple times, under
| [Component], as required, and is part of the [Component]
|* keyword. Different [Circuit Call] keywords can reference the
| same Ext_name or Model_name to describe a different set of
| connections. The [Circuit Call] subparameters are required
| as described below.
|
| Port_map:
| Port_map is followed by a port name and then a node name.
| The port name must be one of the ports in the referenced
| [External Circuit] or [External Model] and must appear only
|* once. However, node names can be repeated to signify a
| connection between ports such as with a common voltage supply.
| The node name may be a die node name or an internal, declared
| node. One Port_map subparameter must exist for each of the
| defined ports in the [External Circuit} or [External Model].
|
| Cell_port, Diff_cell_port, Series_cell_port:
| When the [Circuit Call] keyword names a [Model] keyword,
| either Cell_port, Diff_cell_port or Series_cell_port are
| required.
|
| Cell_port is used when the referenced model uses one I/O port.
| It is followed by a die node name (same as the corresponding
| pin number). Each Cell_port name must be unique for the
| component.
|
| Diff_cell_port is used when the referenced model is a true
| differential model (discussed later). It is followed by two
| die node names (same as the corresponding pin numbers) for the
| differential pins. These names are the non-inverting and the
| inverting die node names. The Diff_cell_port subparameter is
| not used when the differential buffer model is created using
| the [Diff Pin] keyword and independent single-ended models.
| The Diff_cell_port names must be unique and different from any
| Cell_port name for the component.
|
| Series_cell_port is used when the referenced model is a Series
| or Series_switch buffer (discussed later). It is followed by
| two die node names (same as the corresponding pin numbers) for
| the positive and negative pins. The polarity order matters
| only when the passive model is polarity sensitive (as with the
| the [Series Current] keyword). Many Series models can also be
| described directly using the [External Circuit] keyword.
| Series_cell_port names do not have to be unique and can be the
| same as Cell_port or Diff_cell_port names for the component.
|-----------------------------------------------------------------------------
| Circuit Call to model:
|
[Circuit Call] A | References the Model_name of a [Model]
|
Cell_port 1 | Used only for calls to Models.
|
| mapping port node
Port_map A_signal c | Port to internal node connections
Port_map A_puref a
Port_map A_pdref b
Port_map A_pcref d
Port_map A_gcref e
|
[End Circuit Call]
|
[Circuit Call] B | References the Model_name of a [Model]
|
Cell_port 2 | Used only for calls to Models.
|
| mapping port node
Port_map A_signal h
Port_map A_control 3 | Control port to die node
Port_map A_puref f
Port_map A_pdref g
Port_map A_pcref i
Port_map A_gcref j
|
[End Circuit Call}
|
| Circuit Call to die interconnect circuit:
|
[Circuit Call] BUS_SPI | References the Ext_name of an [External Circuit]
|
| mapping port node
Port_map vcc 10
Port_map gnd 11
Port_map io1 1
Port_map io2 2
Port_map vcca1 a
Port_map vcca2 b
Port_map int_ioa c
Port_map vssa1 d
Port_map vssa2 e
Port_map vccb1 f
Port_map vccb2 g
Port_map int_iob h
Port_map vssb1 i
Port_map vssb2 j
|
[End Circuit Call]
|
|=============================================================================
|
| DIFFERENTIAL MODEL FROM SINGLE-ENDED BUFFERS:
|
| The method of specifing differential buffers constructed from single-ended
| models remains the same with or without using the [External Model] keyword.
| The [Diff Pin] keyword is used in all cases, with or without paths defined
| using the [External Circuit] keyword. The method requires using the
| reserved A_signal port.
|
| The reference diagram for each buffer is the same as a single-ended buffer,
| except that the differential connection provided by [Diff Pin] specifies
| connected controls signals and a D_receive signal between two A_signal
| ports:
|
| _____D_enable ___
| | |
| | |\
| | __D_drive____| \_______A_signal (Non-inverting)
| | | | / |
| | | |/ /| |
| | | D_receive____/ |--+
| | | \ |--+
| | | |\ \| |
| | |_____________| \____|__A_signal (Inverting)
| | | /
| | |/
| |_________________|
|
| The D_receive connection is specified through the [Diff Pin] keyword, its
| pin listings and its vdiff subparameter. In addition, the tdelays may be
| inserted in the A_signal paths for relative timing skew modeling. For an
| Input* or I/O* model, each [External Model] must name an A_signal port.
| These ports are implicitly connected to the D_receive as shown in the
| reference diagram.
|
| The [Diff Pin] subparameters determine the polarity reference of D_receive
| according to the pins assigned to the [Diff Pin] and inv_pin columns.
| For example, the Cell_port name for the [Diff Pin] column is the
| non-inverting connection, and the Cell_port name for the inv_pin column is
| the inverting connection. The vdiff value is used to determine the
| D_receive states.
|
| TRUE DIFFERENTIAL MODEL:
|
|* True differential models are supported in IBIS with [External Model] as
|* shown in the reference diagram:
|
| D_enable ___
| |
| |\
| D_drive____| \----+-----A_signal_p
| | /----|--+--A_signal_n
| |/ /| | |
| D_receive____/ |--+ |
| \ |-----+
| \|
|
|* Because the model requires and [External Model] reference, the existing
|* reserved power reference names are not needed. However, this model uses
|* the same reserved port names for single-ended digital control connections.
|* The model developer will need other interfacing circuitry for the D_drive
|* and D_enable signals if differential connections are used to control the
|* model.
|
| Although redundant, the [Diff Pin] keyword can also document which pins the
| differential model is connected. The example below shows how to document
| the A_to_D adapter when vdiff is 200m. Set vlow as -200m and and vhigh as
| 200m. The A_to_D adapter value is required for an I/O* or Input* buffer,
| and the [Diff Pin] vdiff value is ignored.
|-----------------------------------------------------------------------------
| Example of True External Differential SPICE Buffer:
|
[Model] External_Diff_Buffer
Model_type I/O
|
| ... Other model subparameters including C_comp.
|
[External Model]
Language SPICE
| Corner corner_name file_name circuit_name (.subckt name)
Corner Typ diffio.spi diff_io_typ
Corner Min diffio.spi diff_io_min
Corner Max diffio.spi diff_io_max
| Ports List of port names (in same order as in SPICE)
Ports A_signal_p A_signal_n int_in int_en
Ports A_puref A_pdref A_pcref A_gcref
| D_to_A Port port1 port2 vlow vhigh trise tfall
D_to_A D_drive int_in A_gcref 0.0 3.3 0.5n 0.3n
D_to_A D_enable int_en A_gcref 0.0 3.3 0.5n 0.3n
| A_to_D Port port1 port2 vlow vhigh
A_to_D D_receive A_signal_p A_signal_n -200m 200m
|
[End External Model]
|
|-----------------------------------------------------------------------------
|
| RESERVED PORT NAMES:
|
| To promote model interchangeability, the following port names are reserved:
|
| A_signal - I/O electrical connection of a model
| A_signal_p - Non-inverting I/O electrical connection of a differential
| model
| A_signal_n - Inverting I/O electrical connection of a differential model
|
| A_pos - Non-inverting pin of a series model
| A_neg - Inverting pin of a series model
|
| D_drive - Digital drive of a buffer
| D_enable - Digital enable of a buffer
| D_receive - Digital state of a receiver
|
| A_puref - Pullup reference voltage
| A_pcref - Power clamp reference voltage
| A_pdref - Pulldown reference voltage
| A_gcref - Ground clamp reference voltage
|
| A_extref - External reference voltage if applicable
| A_gnd - A global reference voltage, if needed for global ground connection
|
| EXISTING IBIS MODEL SUPPORT:
|
| An existing IBIS model without the [External Model] can be used. The
| reserved port names A_signal and A_pos and A_neg are assumed since they
| are not defined. The [Circuit Call] keyword can be used to connect the
| model directly to the die node or through paths described by the
| [External Circuit] keyword.
|
| A_signal_p and A_signal_n are the reserved port names for true differential
| models (not supported in the existing IBIS format) and require using the
| [External Model] keyword.
|
| EXTERNAL AND INTERNAL REFERENCE VOLTAGES:
|
|* When configuring the interconnection for [Model]s, with or without the
| [External Model] keyword, the external connections for power and reference
| are added AS NEEDED to support the actual model in the external file. If
| such external ports names are not supplied, the necessary reference voltages
|* must be coded in the external file. The [External Model] keyword provides
|* the available ports.
|
|* IBIS [Model]s without the [External Model] keyword will use the internal
|* voltage references. However, external reference voltages will be used
|* whenever the associated [Circuit Call] keyword for that model uses any of
|* the reserved port name voltage references. In this case, all applicable
|* ports must be referenced externally.
|
|* The reference, A_gnd, is implied in existing IBIS models and may also
| appear as a port in certain [External Model]s or [External Circuit]s. If
| A_gnd is not connected, it shall be attached to a global reference, often
| 0 volts. No error is reported for this case.
|
| INTERACTION WITH THE MODEL_TYPE SUBPARAMETER OF [MODEL]:
|
| The Model_type subparameter describes the buffer. The Ports below serve as
| default Port names when only the [Model] keyword is specified without
| [External Model]. When [External Model] is specified, digital port names
| are required for digital control in a manner compatible with other models.
|
| Model_type D_drive D_enable D_receive A_signal* D_switch A_pos A_neg
|
| I/O* X X X X
| 3-state* X X X
| Output*, Open* X X
| Input X X
| Terminator X
| Series X X
| Series_switch X X X
|
| Series and Series_switch devices can be described using the [External Model]
| keyword as polarity sensitive, two-terminal models. The reserved signal
| names A_pos and A_neg are assumed if such a device is defined with exiting
| IBIS syntax without [External Model]. The reserved names are needed for
| connecting the model through an [External Circuit] path. The A_pos
| connection is the die node (pin) defined by the first column of the [Series
|* Pin Mapping] keyword, and the A_neg connection is to the die node (pin)
|*defined in the pin2 column. However, the A_pos and A_neg port names are not
|*required when [External Model] is used because the necessary connections are
|* made directly.
|
| Any [Circuit Call] keyword that names a [Model] for a Series_switch or
| Series device must also use Series_cell_port to name the corresponding die
| nodes. The Series_switch models still need to reference the die nodes to
| control the D_switch setting, where '0' is Off and '1' is On.
|
| For Series devices, an [External Circuit] keyword can be used to avoid the
| need for the Series_cell_port subparameter in the corresponding reference
| by [Circuit Call].
|
| COMPONENT MEASUREMENT LOCATIONS:
|
| The [Component] keyword contains the subparameters Si_location and
| Timing_location. The arguments are 'Pin' and 'Die'. The 'Pin' argument
| will continue to be interpreted as the pin side of the package model. The
| 'Die' argument will be interpreted to mean the connection to the A_signal*
| port of the model. This is consistent with the existing interpretation if
| no [External Circuit] path exists between the A_signal* connection and the
| die node. When such a path exists, the 'Die' location is close to the
| active silicon terminal where the measured voltage will control the
| electrical operation.
|
|*
|* Description 2 (per IBIS Futures Group recommendation)
|*
| REGISTERING MODELS:
|
| The [Pin] keyword subparameter model_name is used to register [Model]s and
| signify a direct connection to the die node. The model_name is still
| entered when a model or any part of it is connected by the [Circuit Call]
| keyword. This name must match the corresponding model_name referenced in
| the [Circuit Call] keyword for the die nodes (pins) named by Cell_port or
|* Diff_cell_ports. The model_name reference under the [Pin] keyword is
|* redundant, but it serves to document the signal port connections of each
|* [Model] to each die node for all direct or indirect connections.
|
|-----------------------------------------------------------------------------
| Example of Registration:
|
[Pin] signal_name model_name R_pin L_pin C_pin
|
1 A A | Models A and B are connected through [External
2 B B | Circuit] and [Circuit Call] keywords
3 Control_pin NC | Control_pin connection is though [Circuit Call]
| ... | to a circuit outside of the component
10 POWER POWER
11 GND GND
| ...
|-----------------------------------------------------------------------------
|
| KEYWORD INTERACTION LIMITS:
|
| Because the set of features in this section expand connection options and
| extend functionality, some IBIS keyword limitations exist when using
| [External Model] and/or [External Circuit]. New limitations for Version 4.0
| are noted. Not all conflicting information can be checked.
|
| [Model Selector]:
| The [Model Selector] keyword should be avoided since it can reference
| another [Model] having a different set of Port names that are not
| compatible with the related [Circuit Call] keyword.
|
| [Pin Mapping]:
| The [Pin Mapping] keyword can provide conflicting information with
| [Circuit Call] and does not support the more general networks that
| [External Circuit] supports. If necessary, the [Pin Mapping] busses
| can be expressed using the [External Circuit] keyword.
|
| [Diff Pin]:
| The [Diff Pin] keyword is ignored when [External Model] used to
| configure a true differential structure since all the information is
| available in the [External Model] and the associated [Circuit Call]
| keywords and Diff_cell_port subparameter.
|
| [Series Pin Mapping], [Series Switch Groups]:
| The [Series Pin Mapping] keyword is ignored when [External Model] is
| used to configure a Series two-pin structure. The necessary connection
| associations are with contained in the [Circuit Call] keyword and
| Series_cell_port subparameter.
|
| However, Series_switch models using the [External Model] keyword still
| need the [Series Pin Mapping] keyword to define the associations with
| with die nodes (pins) and the function_table_group subparameter. The
| appropriate settings that control D_switch are then available using
| the [Series Switch Groups] keyword.
|
| It is possible to use the [External Circuit] for similar connectivity
| without needing [Series Pin Mapping] or [Series Switch Groups], but
| the switching configurations would have to be set up on a case-by-case
|* basis in each EDA tool.
|
| [Model] keywords when using [External Model]:
| Replaces all keywords under [Model] except [Model Spec], (Version 3.2)
| Replaces all new keywords under [Model] except [Receiver Thresholds],
| [External Reference] (unless using A_extref), [Test Data], and
| [Test Load]. (Version 4.0)
| Replaces C_comp subparameter. (Version 3.2)
| Replaces the C_comp_pullup, C_comp_pulldown, C_comp_power, and
| C_comp_gnd subparameters. (Version 4.0)
|
|=============================================================================
******************************************************************************
ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:
The IBIS-X Macro-language activity is addressing the extended model behavior
problem. However, its solution depends upon a new syntactical macrolanguage
which will take time to debug and implement. While a single, common
macro-language is highly desirable, An alternative, simpler, shorter term
path that leverages off industrially accepted public formats and standards
will also address the industrial needs in a very IBIS compatible manner.
Two types of languages that lend themselves to extending IBIS: SPICE and
various hardware description languages with analog/mixed signal extensions.
While either type of language can be used for all extensions, SPICE formats
are particularly strong for electrical interconnect extensions and structural
device descriptions while the hardware description languages are particularly
strong in equation handling and behavioral/logical extensions.
At this time Berkeley SPICE, VHDL-AMS and Verilog-AMS are the proposed
targeted extension languages. This is based on several desirable criteria:
Applicable to electrical circuit, device, and modeling issues
Open, publicly available format
Widely used, either directly or through emulation
Controlled under an official standardization group or independent body
Language is stable and is expected to remain downward compatible
The official IBIS list should not include vendor-specific implementations,
extensions, or deviations even if they are widely used. Vendors can deal
this issue by non-compliant IBIS extensions or interpretations.
These criteria are intended to limit the support of many language formats
(especially private de facto formats) to maximize model interoperability.
Berkeley level 3F5, VHDL-AMS and related extensions, and Verilog-AMS appear
to meet the above criteria. Verilog-AMS is still being processed for formal
IEEE standardization. So, the reference recognizes that the language call
will eventually mean the full, officially approved version.
Berkeley SPICE 3F5 is no longer readily available. However, it has served as
the basis of a number of commercial implementations that it still serves as a
SPICE baseline reference. Berkeley SPICE 2G6 could also have served as a
base, but it contains numerical node naming restrictions and other
restrictions that are not seen in practice.
External language syntax is not embedded within .ibs files because in most
tools such syntax would have to be exported into separate files in order for
the EDA tool to test and process it without syntactical errors.
BIRD75 was reviewed by the IBIS Futures Working Group, and a number of choices
already resolved are reflected in this BIRD75. Two Registration choices are
given for discussion. Description 1 supports possible future EBD style
syntactical expansion where several models can be associated with a die node
(pin). Description 2 supports existing IBIS conventions with a tight
association of a specific model_name to a pin number, even if there are added
electrical paths on the die.
BIRD75.1 has some editorial corrections. The Registration option below
is captured
|*
|* Description 1
|*
| REGISTERING MODELS:
|
| The [Pin] keyword subparameter model_name is used to register [Model]s and
| signify a direct connection to the die node. However, the model_name entry
| must be NC when a model or any part of it is connected by the [Circuit Call]
| keyword. Normally, this convention is used to distinguish direct die node
| connections from indirect die node connections that occur through paths
| given by the [External Circuit] keyword. However, NC can also be optionally
| used with [Circuit Call] even if the connections (A_signal* ports) are made
| directly to the die nodes. The [Circuit Call] keyword provides both the
| model_name and Cell_port (or Diff_cell_port) die nodes, so NC is entered
| under the [Pin] keyword to avoid redundant information.
|
|-----------------------------------------------------------------------------
| Example of Registration:
|
[Pin] signal_name model_name R_pin L_pin C_pin
|
1 A NC | Models A and B are connected through [External
2 B NC | Circuit] and [Circuit Call] keywords
3 Control_pin NC | Control_pin connection is though [Circuit Call]
| ... | to a circuit outside of the component
10 POWER POWER
11 GND GND
| ...
|-----------------------------------------------------------------------------
The futures group stated that they preferred the model name in the pin
list, even if it is redundant. BIRD75.1 documents this is Description 2.
******************************************************************************
ANY OTHER BACKGROUND INFORMATION:
BIRD75 is follow up to an introductory given at the IBIS Summit Meetings
on January 28, 2002 and March 8, 2002.
******************************************************************************
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