Subject: [IBIS] Minutes, IBIS Open Forum Summit 10/15
From: Peters, Stephen (stephen.peters@intel.com)
Date: Thu Oct 17 2002 - 11:48:07 PDT
Date: 10/17/02
SUBJECT: October 15, 2002 EIA IBIS Open Forum Summit Minutes
VOTING MEMBERS AND 2002 PARTICIPANTS LIST:
Ansoft Corporation (Eric Bracken)
Apple Computer Kim Helliwell
Applied Simulation Technology Fred Balistreri, Norio Matsui
Cadence Design Lynne Green*, Patrick dos Santos, Lance Wang*
Cisco Systems Syed Huq, Abdulrahmun Rafiq, Zhiping Yang,
Mike LaBonte*, Todd Westerhoff*
Cypress Semiconductor (Rajesh Manapat)
Huawei Technologies (Jiang Xiang Zhong)
IBM Greg Edlund*, Pravin Patel
Innoveda (Merged with Mentor John Angulo, Guy de Burgh, Steve Gascoigne
Graphics)
Intel Corporation Stephen Peters*, Arpad Muranyi*, Will Hobbs,
Pete Block, Ben Silva, Tony Lewis,
Michael Mirmak
LSI Logic [Larry Barnes], Frank Gasparik
Matsushita (Panasonic) Atsuji Ito
Mentor Graphics Bob Ross*, Ian Dodd*, Mike Donnelly,
Matt Hogan, Sherif Hammad, [Tom Dagostino],
Eric Rongere, Karine Loudet, Kevin Cohan*
Micron Technology Randy Wolff
Mitsubishi Pat Hefferan
Molex Incorporated Gus Panella
Motorola Rick Kingen
National Semiconductor Milt Schwartz
NEC Corporation (Akimoto Tetsuya)
North East Systems Associates Edward Sayre*, Kathy Breda*
Philips Semiconductor (D.C. Sessions)
Quantic EMC (Mike Ventham)
Siemens (& Automotive) AG Helmut Katzier, Katja Koller, Eckhard Lenski
Signal Integrity Software Barry Katz*, Walter Katz, Robert Moles,
Daniel Nilsson, Kevin Fisher, Steve Coe,
Wiley Gillmor, Douglas Burns, Eric Brock,
Bob Haller*
Sigrity Raj Raghuram
SiQual [Scott McMorrow], Dave Macemon, Rob Hinz
Texas Instruments Thomas Fisher*, Jean-Claude Perrin
Teraspeed (Scott McMorrow), Tom Dagostino*
Time Domain Analysis Systems Steve Corey, Dima Smolyansky
Via Technologies (Weber Chuang)
Zuken (& Incases) Caroline Legendre, Ralf Bruening
OTHER PARTICIPANTS IN 2002:
3Com (& CommWorks) [Roy Leventhal], James Goshorn
Actel Prabhu Mohan
Agilent Herbert Lage*
Airbus Claude Huet
Alstom Transport Luca Giacotto*
Apt Software Atul Agarwal
Astrium Olivier Prieur
Bee Technologies Corporation Tsuyoshi Horigome
Brocade Communications Robert Badal
Compaq Shafier-ur-Rahman
EADS CCR Alix de la Villeguerin
EFM Ekkehard Miersch
EIA [Cecilia Fleming], Chris Denham
EMC Corporation Brian Arsenault*, Jeanne Hereth*,
Elena Gutman*, Julian Simbu*
Fairchild Semiconductor Adam Tambone
Force Computers Roger Sukiennik
Harman/Becker Automotive Hartmut Exler
Systems
Hatachi Nonoyama Sadahiro*, Shoji Kazuyoshi*
Japan Electronics and Kiyomi Daishido
Information Technology
Industries Association
(JEITA)
Leventhal Design and Roy Leventhal
Communication
National Institute of Applied Sebastian Calvet (& Motorola)
Science (INSA) Etienne Sicard, Stephane Baffreau
Northrup (Litton) Robert Bremer
Sagam SA Quang Ngo, Matthieu Fontaines
Shindengen Elecric Mfg. Co. [Tsuyoshi Horigome]
Sintecs Hans Klos
STMicroelectronics Fabrice Boissieres
Synopsys (Avanti) (Hailong Wang)
TDK Yoshikazu Fujishiro
Thales Saverio Lerose
Tyco Electronics (Tim Minnick)
UTMC Greg Haynes
Xilinx Susan Wu, J.L. de Long
Independent Larry Barnes
In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.
Upcoming Meetings: The bridge numbers for future IBIS teleconferences are
as follows:
Date Bridge Number Reservation # Passcode
November 1, 2002 (916) 356-2663 2 2855166
All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.
NOTE: "AR" = Action Required.
-------------------------------- MINUTES -----------------------------------
The fifth annual IBIS East Summit Meeting was held on October 15, 2002 at
the North East Systems Associates offices in Westford, Massachusetts, in
conjunction with the PCB Conference East in Boxborough Massachusetts.
Because of general industrial travel restrictions, a phone bridge and
optional web cast link were setup by Intel Corporation.
A total of 24 people representing 13 organizations participated. Seven of
the participants attended by telephone.
INTRODUCTIONS AND BUSINESS
Stephen Peters welcomed the participants and thanked North East Systems
Associates (NESA), Cadence Design Systems, Intel Corporation, the IBIS Open
Forum and the IBIS Users group for there support in co-sponsoring the
summit. Stephen also thanked Kathy Breda and NESA for handling the
administrative and logistical details, and Cadence for supplying for the
delicious pre-meeting lunch. Stephen also thanked Arpad Muranyi from Intel
for enabling the web based presentations. Finally, Stephen noted that
questions and interactive discussion was encouraged.
All of the presentations and meeting documentation were available at the
meeting and were also uploaded to the IBIS web site at:
http://www.eda.org/pub/ibis/summits/oct02/ or
http://www.eda.org/pub/ibis/summits/
Stephen stated that there were no business issues. Stephen asked for any
open topics. None were offered.
KEYNOTE REMARKS
Stephen Peters introduced Ed Sayre, Chair of the IBIS Users Group for some
keynote remarks.
Ed stated that IBIS is now a key ingredient for success in industry. While
IBIS quality remains an issue, it is being addressed. Ed believes that the
interconnect specification will become extremely important to the industry,
along with the ability for IBIS to contain many different types of models.
On the subject of IBIS versus SPICE models, Ed noted that the "best" model
depends on the application. Ed also felt that tools should be categorized
by application, not what models the tool runs. Ed remarked that the
industry does not need religious wars between SPICE and IBIS, the issue is
selecting the 'correct hammer for job'.
Ed expressed the concern that as each version of IBIS is released the syntax
is becoming more and more specialized. He cautioned the Open Forum that it
is important to keep the syntax clean and self-consistent. Finally, Ed
noted that the vast majority of problems don't require models that use the
complete IBIS feature set.
PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions. These
notes capture some of the content and discussion. See the uploaded
documents for more detail.
IBIS STATUS REPORT
Stephen Peters, Intel Corporation
Presenting via telephone, Stephen began his presentation by stating that
the organization remains a strong and relevant force in the industry. We
continue with 30 paid members, and the IBIS quality group is aggressively
and successfully addressing the industry wide issue with model quality. In
addition, over the last few months there has been active discussion on the
multi-lingual modeling proposal (BIRD75), with a vote scheduled during
the next regularly scheduled IBIS teleconference. Stephen expects BIRD75
to significantly extend the life of IBIS modeling.
On the subject of IBIS 4.0 parser development, Stephen announced that we
have selected (subject to ratification by the Open Forum) Atul Agarwal
as the parser developer. The winning bid was for $25,000. On the
downside, Stephen noted that the money we had set aside from previous years
to pay for parser development is no longer available. The result is that
the IBIS Open Forum will have to raise substantially more money from the
member companies than was expected. Stephen stated that the parser funding
issue will be fully discussed at the next teleconference meeting.
Finally, Stephen noted that the long awaited IBIS Interconnect Modeling
(ICM) specification has been released for review, and that work continues
on adding EMI and EMC support to IBIS.
The question was asked if the parser price included development of a parser
for the interconnect specification. Stephen replied that the quoted price
was for development of the IBIS 4.0 parser only. Ed Sayre then asked the
EDA vendors what their plans were for supporting IBIS 4.0 features. Both
Mentor Graphics and Cadence responded that they plan support next year or
in the next release.
IBIS INTERCONNECT SPECIFICATION
Stephen Peters, Intel Corporation
Stephen opened this presentation by noting that a draft version of the
Interconnect Specification (ICM version 1.0) has been released for
review and is available on the IBIS web site under the "connector
Info" link.
http://www.eda.org/pub/ibis/connector/
So far, one extensive comment on the specification has been received.
Although there were no feature changes or additions to the specification
since the last update in June 2002, some minor technical and wording issues
were resolved. Moving forward, Stephen stated that the next step is to
figure out how to pay for ICM parser development. Stephen also mentioned
that the ICM specification can be used with the proposed multi-lingual
modeling bird to provide a complete model of the interconnect from the
die on thru the package.
In a quick overview of the technical details, Stephen stated that the
specification supports a single interconnect family; a family consists of
one or more individual models. Models are described in terms of such basic
information as maximum slew rate allowed, the model type (single line or
multi-line model), a path description, and information that allows the EDA
tool to map model pins to the rows of an RLGC or S-parameter matrix.
Stephen also noted that the specification supports three different types
of interconnect -- regular (no pins missing) and rectangular, regular and
non-rectangular, and irregular. Only regular interconnect is swathable.
Multi-line models (MLM) contain full coupling between pins or traces and are
intended to be used for simulations involving crosstalk and ground return
paths. On the other hand, single line models (SLM) do not support crosstalk
information and are primarily intended to model a pin under specific
conditions. Several different types of SLMs are available, including ones
created under even-mode, odd-mode and quiescent switching conditions.
Stephen noted that, for these models, the ground return path used to derive
the models values are documented in the models pin map.
Finally, Stephen pointed out that the data in the RLGC matrices can be
interpreted as either lumped elements or as per-unit-length values. This
interpretation is determined by a "Len" or "Mult" argument in the
path description and the [Derivation Method] keyword in the matrix section.
Lumped elements result from 3-D field solver extraction of irregular
structures, and are suited for describing most connectors. "Lump size" is
determined by the model created, and is based upon the maximum risetime the
connector is expected to support. On the other hand, per-unit-length values
result from 2-D field extraction and are suited for describing the parallel
traces in a package. Per-unit-length values are expected to be used in a
distributed transmission line model.
Ed Sayre asked how time domain simulators were expected to use the frequency
based S-parameters matrix. Arpad Muranyi replied that there are numerical
techniques that make S-parameters usable in a time domain simulator. In
the reverse case, a frequency domain simulator can always take an IBIS
model, find the DC operating point, then linearize the model. In the
following discussion it was noted that while most SI simulators are time
domain based, there are free to incorporate and use frequency domain based
models and techniques.
Brian Arsenault from EMC asked how much support there is among the connector
vendors for the ICM spec. Stephen replied that Gus Panella from Molex was
very active in defining the specification, so there is at least one
connector vendor interested. Stephen stated, however, that he would like
to see more than one vendor release ICM models.
IBIS QUALITY COMMITTEE REPORT
Barry Katz, Signal Integrity Software (SiSoft)
Barry began by presenting data on the number of downloadable IBIS files
that contain errors. Barry also made the point that even if a file passes
IBISCHK3 with no warnings or errors the model may still not be usable.
The parser doesn't capture everything that makes a good model. Recognizing
this fact, the quality committee was formed. Its charter is to develop
a checklist that defines levels of IBIS model quality and is usable
by purchasing and procurement organizations. The committee was also tasked
with suggesting enhancements to the current IBISCHK3 parser. Barry noted
that the goal of any quality rating system is ease of use and understanding.
This is important because these specifications have to be communicated
to non engineers.
Barry mentioned that the quality committee, which meets every two weeks,
includes participants from Europe, US and Japan. Barry went on to
announce that the IBIS Quality Checklist is available at
http://www.sisoft.com/ibis-quality/
Kevin Cohan asked if the quality level of a file is established by the
component as a whole or by each individual model. Barry replied that this
is open for discussion, but that in general all models in a component must
be at level 1 for the component to be at level 1. Barry went on to note
that at a minimum all models should parse with no errors and no warnings.
Arpad Murani asked if this applies to version 1.1 and 2.1 models as well.
In the following discussion it was noted that different versions of the
parser check for different things, and it may be impossible to get
earlier versions of the parser to a 'no warning' standard. The question
was also asked if it was appropriate to fix non-monotonic warnings.
According to Tom Dagostino, there are logic families that contain
outputs with non-monotonic I-V characteristics and the 'no-warning/no-error'
standard may not apply to these components. A model creator must be aware
of them and document them appropriately.
The quality checklist documents four levels of quality. A Level 0 model
passes the parser and includes the data required to do a timing analysis
(values for Vinh and Vinl as well as the timing test loads). Level 1 models
are complete and correct with various levels of detail, including visual
inspection of I-V and V-T tables. Also, to be classed as level 1 the model
must have been run thru a simulator. It was noted that the model creator
should document what simulator ran model in. Level 2 models addresses the
correlation of models to SPICE or silicon and leverages off the work of
the accuracy committee. Level 3 models are correlated to both silicon and
SPICE.
Stephen Peters asked if the quality committee has considered taking on the
task of updating the s2ibis2 program. The committee has not discussed
this, and suggested that this may be better handled by a new subcommittee.
MEASUREMENT BASED MODELING
Tom Dagostino, Teraspeed Consulting Group LLC
Tom stated that there are several advantages to creating IBIS models from
measurement. Chief among them are the ability to create a model without
having to obtaining a Non-disclosure agreement (NDA) and the ability to
create a model without needing access to a semiconductor companies
proprietary SPICE. Tom stated that it is also relatively easy to measure
the AC and DC characteristics of a device to the accuracy required (1% DC,
>10Ghz bandwidth AC). However, Tom noted that AC measurements are limited
by the probing and fixturing. Tom contend that anything you can do with
SPICE you can do with SPICE, and in response to a question he stated that he
does have a measurement approach to multi-stage outputs. If min/typ/max
models are needed then access is required to full process silicon.
The required equipment includes a high bandwidth sampling scope, various
power supplies and a word generator (stimulus source) that is compatible
with the standard logic families (CMOS, ECL, PECL, CML, etc.) In response
to a question, Tom stated that he uses a TDR for measuring C_comp, however
one can also use a VNA. Arpad Muranyi then asked how the outputs of a
complex chip are put into the correct logic state for I-V and V-T
measurements. Tom replied that, when available, he uses the JTAG port to
control output buffer state.
Tom controls the hardware setup via a software program that also writes
the models. The measurement process starts with V-T data collection into
the standard 50 ohm loads, followed by I-V data acquisition. I-V data is
collected by sweeping the output with a variable supply. Arpad Muranyi
asked if he has seen any variations or errors because of die self heating.
Tom replied that he has not seen much I-V data variation due to this effect.
Tom did note that out of the 17,000 parts he has modeled, 98% of them have
been at typical.
Tom then asked the audience if models that include temperature and voltage
variations but not process variations are useful. Ed Sayre replied that
in real systems temperature variations across a chassis are a big variable,
so models of this type would be very useful. Arpad Muranyi also pointed
out that many buffers incorporate compensation circuits that adjust their
output impedance based on temperature, so models created at various
temperatures may be required in order to do real corner testing.
Finally, Stephen Peters asked how the effects of packaging are de-embedded
from the V-T data. Arpad mentioned that this could be done numerically.
Tom replied that he does not try and de-embed package effects from the
V-T data, and it would take several TDR/TDT measurements to characterize a
package.
SPICE VERSUS IBIS
Bob Haller, Signal Integrity Software (SiSoft)
Bob opened his presentation by stating that contrary to popular belief
one can create IBIS models that produce waveforms which overlay
waveforms generated by transistor level SPICE circuits.
Bob noted that SPICE models can be accurate because they model such effects
as rail collapse, ground bounce and other buffer effects that are not
covered by IBIS. Return paths can also be modeled using SPICE, although
Stephen Peters contended that modeling return paths was a tool capability
issue, not an IBIS issue. Disadvantage to using SPICE are performance and
inconsistencies between various versions. There was a long discussion
regarding how various SPICE vendors qualify there models and the tendency of
users to use only the SPICE version that the model was qualified under.
On the other hand, IBIS models don't reveal proprietary information and they
give a complete description of the component level pin out and AC/DC specs.
Disadvantages to using IBIS are the industry quality issues, and the
previously mentioned limitations on packages. Also mentioned was the
simplistic model for C_comp modeling, and the amount of time it takes to
get things thru the IBIS committee.
In the discussion that followed Stephen Peters asked if anyone was able to
comment on practical limit to the I-V / V-T methodology of behavioral
modeling. Arpad Muranyi mentioned that he is seeing buffers that employ
de-emphasis circuits that interact with standard I-V curves in ways that
may not be capturable by I-V curves alone. Ed Sayre also mentioned the
difficulty of de-embedding V-T data thru a package.
In summary, Bob states that the industry need both SPICE and IBIS models,
and the Open Forum must keep pushing forward.
MORE DETAILS ON TRUE DIFFERENTIAL BUFFER CHARACTERIZATION
Arpad Muranyi, Intel Corp. (presentation delivered via telephone)
Arpad presented a follow-up to the presentation given by Hazem Hegazy at
the January 2001 and March 2001 IBIS summits on how to model differential
models using single ended IBIS buffers. In the previous presentations,
Hazem pointed out weakness in Aprad modeling methodology, and presented
a method that relied on determining both the differential and common mode
currents. In this presentation Arpad proposes generalizing Hazem's method
by using the [Series Pin Mapping] keyword to include components that mimic
the differential currents of a true differential buffer.
Arpads proposed method is to sweep the voltage and measure current on one
pin of the differential output, then step the voltage on the other pin and
repeat the sweep. The result is then plotted on a 3-dimensional plot (a
surface plot in Excel). The surface plot is used to both visualize the
currents as well as separate the common mode current from the differential
currents in a buffer. This is done by normalizing the Ipin1 vs. Vpin1 vs.
Vpin2 plots to the common mode current. The resulting plot is a plot of the
difference current. As a proof that this method works, Arpad first
showed the surface plot of a buffer with a 1.4Kohm output impedance in the
operating region. He then added a 100 ohm resistor across the output. The
surface plot now showed that the output impedance of the buffer was 93
ohms, with is the parallel combination of 1.4Kohm and 100 ohm. Finally,
while it may appear that multiple I-V curves are required to implement this
method, in the operating region the difference current is linear enough
to be represented by a fixed resistance, thus the use of the [R_series]
keyword.
Arpad noted that further study is required on developing a method to
extract differential C_comp. In additon, experiments designed to figure
out how differential current varies with respect to time are required.
Arpad also urged CAE vendors to implement the series element keywords as
soon as possible.
Finally, Barry Katz offered that the method offered by Arpad was the
mathematically correct way to represent a differential buffer.
CLOSE OF MEETING
Stephen again thanked the participants for their contributions and thanked
the co-sponsors.
NEXT MEETING:
The next teleconference meeting will be on Friday, November 1, 2002 from
8:00 AM to 10:00 AM Pacific time. A vote on BIRD75.6 and BIRD77.2 is
scheduled.
============================================================================
NOTES
IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
stephen.peters@intel.com
Senior Hardware Engineer, Intel Corporation
M/S JF4-215
2111 NE 25th Ave.
Hillsboro, OR 97124-5961
VICE CHAIR: Lynne Green (425) 788-0412, Fax (425) 788-4289
lgreen@cadence.com
Senior Modeling Engineer, Cadence Design Systems
20 120th Ave NE, Suite 103, Bellevue, WA 98005-3016
SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
guy_deburgh@mentor.com
Senior Manager, Mentor Graphics
1369 Del Norte Rd.
Camarillo, CA 93010-8437
LIBRARIAN: Roy Leventhal (847) 590-9398
roy.leventhal@ieee.org
Consultant, Leventhal Design and Communications
1924 North Burke Drive
Arlington Heights, Illinois 60004
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008
John_angulo@mentor.com
Development Engineer, Mentor Graphics
14715 N.E. 95th Street, Suite 200
Redmond, WA 98052
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