Subject: [IBIS] IBIS Summit minutes (06/05/03)
From: rrwolff@micron.com
Date: Mon Jun 09 2003 - 17:06:02 PDT
DATE: 6/9/02
SUBJECT: June 5, 2003 EIA IBIS Summit Meeting Minutes
VOTING MEMBERS AND 2003 PARTICIPANTS LIST:
Ansoft Corporation (Eric Bracken)
Apple Computer Kim Helliwell*
Applied Simulation Technology Fred Balistreri
Cadence Design Lynne Green*
Cisco Systems Syed Huq*, Val Mandruson, Hung Pham
Cypress Semiconductor (Rajesh Manapat)
Fairchild Semiconductor (Graham Connolly)
Hitachi ULSI Systems Kazuyoshi Shoji
Huawei Technologies (Jiang Xiang Zhong)
IBM (Pravin Patel)
Intel Corporation Stephen Peters*, Michael Mirmak*,
Arpad Muranyi*, Eric Magnusson
LSI Logic Frank Gasparik
Matsushita (Panasonic) Atsuji Ito*
Mentor Graphics [Bob Ross], Ian Dodd, Guy de Burgh*,
John Angulo*, Mike Donnelly, Weston Beal
Micron Technology Randy Wolff
Mitsubishi (Pat Hefferan)
Molex Incorporated Gus Panella
Motorola (Rick Kingen)
National Semiconductor [Milt Schwartz], [Tim Coyle]
NEC Electric Corporation (Itsuki Yamada)
North East Systems Associates Edward Sayre
Philips Semiconductor (D.C. Sessions), Stephanie Goedecke
Quantic EMC (Mike Ventham)
Siemens (& Automotive) AG Eckhard Lenski, Michael Kindij,
Burkhard Muller, Katja Koller,
Andre Goerisch, Manfred Maurer,
Bernard Unger, Amir Motamedi,
Hartmut Ibowski, Gerald Bannert
Signal Integrity Software Bob Haller, Barry Katz, Doug Burns
Sigrity [Raj Raghuram]
SiQual (Rob Hinz)
Synopsys Warren Wong*, Edmund Cheng*
Texas Instruments Thomas Fisher*
Teraspeed Scott McMorrow, Tom Dagostino,*
Kevin Simpson, Bob Ross*
Time Domain Analysis Systems Dima Smolyansky*, Steve Corey*
Via Technologies (Weber Chuang)
Zuken (& Incases) Michael Schaeder, Ralf Bruning*
OTHER PARTICIPANTS IN 2003:
Agilent Technologies Herbert Lage
Brocade Frank Yuan, Yongrue Yu
Conexant Gary Felker
EADS CCR Alix de la Villeguerin
EFM Ekkehard Miersch
EMC Corporation Brian Arsenault
Fraunhofer IZM Ege Engin
Fujitsu Tadashi Arai
GEIA (Chris Denham)
Idaho State University Al Davis*
Independent Kelly Green, Luca Giacotto*
Infineon Tech AG Christian Sporrer
Marvell Semiconductor Itzik Peleg
NetLogic Microsystems Eric Hsu
Plexus Joseph Socha
Politechnico de Torino Igor Stievano
Qlogic Larry Barnes
Sintecs BV Hans Klos, Bob te Nijenhuis
Sun Microsystems Tim Coyle
Xilinx Susan Wu
In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.
Upcoming Meetings: The bridge numbers for future IBIS teleconferences
are as follows:
Date Bridge Number Reservation # Passcode
June 23, 2003 DesignCon East Summit, teleconference TBA
June 27, 2003 (916) 356-2663 1 1321085
All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.
NOTE: "AR" = Action Required.
-------------------------------- MINUTES -----------------------------------
INTRODUCTIONS AND MEETING QUORUM
The IBIS Summit Meeting was held in Anaheim, California at the Anaheim
Marriot Hotel in conjunction with the Design Automation Conference
(DAC2003). The summit was co-sponsored by IBIS and Cadence Design Systems.
About 19 people representing 12 organizations attended.
The notes below capture some of the content and discussions. The meeting
presentations and other documents are uploaded at:
http://www.eda.org/pub/ibis/summits/jun03a/
Stephen Peters asked everyone in the room to introduce themselves. The
group was well-attended by semiconductor vendors and model providers,
EDA tool vendors and users of IBIS models. Stephen thanked Cadence Design
Systems for co-sponsoring the summit as well as Mentor Graphics for making
the hotel room arrangements and supplying the LCD projector. Finally,
Stephen thanked the presenters and participants for attending.
Stephen asked if there were any new issues or discussion items to put on
the agenda. Lynne Green asked to discuss arrangements for the upcoming
IBIS summit at DesignCon East.
PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions. These
notes capture some of the content and discussion. More details are
available in the documents uploaded to the location noted above.
IBIS ANNUAL REPORT
Stephen Peters, Intel Corporation
Stephen opened the presentations with a summary of today's meeting,
a look back at the previous year, and a look ahead at the coming years'
challenges. Stephen noted that IBIS 3.2 is truly an international
standard, as evidenced by European and Japanese interest, and that,
despite the weak economy, the IBIS Open forum membership remained constant
at about 24 paid members. The organization remains financially healthy.
Significant events this year included the passage of IBIS 4.0, the adoption
of multi-lingual modeling, and the introduction of the Interconnect
Modeling (ICM) specification for review by the forum. The biggest
challenges for the coming year include enabling the future roadmap by
passing IBIS 4.1 and adoption of the ICM Specification. In addition,
Stephen stressed the need for an updated IBIS cookbook and providing
AMS modeling guidance to the industry. The IBIS Open Forum must also
continue to work to improve model quality. Stephen would also like to
continue to track European EMC/EMI developments and determine the need
for XML based parsers. Finally, Stephen offered his thanks to the officers
and other members of the organization for their support and help during
the past year.
IBIS QUALITY COMMITTEE UPDATE
Kim Helliwell, Apple Computer
Kim began his presentation by noting that, as cycle times decrease and edge
rates increase, quality models are becoming more important. On recent
accomplishments, the committee has completed review of seven of the 10
quality document sections. In addition, BUG 71 dealing with non-monotonic
error due to individual I-V table checking has been passed. Kim noted that
this was the most common warning from the parser, and with the parser now
checking summed tables this warning will now have meaning.
Kim reviewed the IBIS quality levels, noting that for a model to be valid
at a level then it must have passed all previous levels. Arpad Muranyi
asked if a level 3 model must have passed both level 2a and 2b. Kim replied
that a level three model must pass both. In follow-up questioning,
Kim clarified that the spice simulation models must be correct.
Regarding future items, Kim noted that there are 3 documents left to review
(VT curves and ramps, model correlation, and possible errors). Lynne Green
will be compiling the sections into the final documentation, and the plan
is to have this effort completed for review in time for the IBIS East summit
meeting in October, 2003. Finally, Kim mentioned that the committee is
interested in feedback on the document, even on the chapters that have
not been completed.
For additional information on the quality committee and to be included on
the mailing list send mail to ibis-quality@freelist.org. The IBIS quality
committee web site is available on the IBIS web page or at
http://www.sisoft.com/ibis-quality
ICM STATUS AND UPDATE
Michael Mirmak, Intel Corp
Michael stated that the purpose of the IBIS Interconnect Modeling
Specification (ICM specification) is to establish a human-readable
standard format for exchanging interconnect modeling data. At a high level,
the specification uses a two part format. The first part describes the
model in terms of a 'section', with sections either joined in a tree
arrangement according to implicit connections or in a nodal arrangement with
explicitly described nodes. The second part of an ICM file supplies
the electrical data for each section. Electrical data is in the form of
either RLGC matrices or S-parameters.
Michael noted that since September, 2002 over 63 issues have been formally
logged. Most were editorial changes, but there were also some technical
limitations and clarifications added. RLGC and S-parameter sections are
not permitted within the same model. S-parameter data is only to be used
with the [Nodal Path Description] keyword.
Michael noted that the draft 1.0 specification was officially introduced at
the May 30, 2003 meeting and a parser is in development. Michael asked for
example models from the summit participants.
Some technical advancements have been proposed for future revisions.
One suggestion would permit mixing RLGC and S-parameter data within a
single model description. Requests have also been made to include support
for frequency dependent RLGC matrices. Enhancements and BUGS will be
handled by a process similar to the existing BIRD process for the IBIS
specification. For the longer term, suggestions have been made that
explicit links between IBIS and ICM be made in one or both specifications.
At present, tools are implicitly assumed to handle the use of ICM models as
package data for IBIS models. A larger issue involves Touchstone(R)
support for mixed-mode S-parameters. At present, Touchstone(R) is
understood to support only standard single-ended S11, S12, etc.
S-parameters. While the format can be used to distribute mixed-mode data
(SDD12, SCD22, etc.), the specification includes no guidance for users or
tools for interpreting the placement of the data points in a standard way.
Finally, Michael mentioned that to best support and encourage ICM usage,
a cookbook is needed.
Michael closed his presentation by noting that the quickest way to achieve
an official specification is to provide feedback on the draft and example
models for parser testing. He thanked the past contributors and present
Connector Subcommittee members for their assistance in producing the ICM
specification.
Stephen asked the group regarding their interest in mixed-mode S-parameters.
Steve Corey stated that TDA had similar questions regarding Touchstone(R)
when TDA Systems built their parser software. Steve saw a need for
explicitly supporting mixed-mode, but had no immediate suggestion on the
best way to do so. Michael mentioned that the driving force behind mixed
mode is the prevalence of differential signaling technologies, such as USB,
SATA, LVDS and the upcoming PCI-Express. Currently, multi-mode (more than
two ports) descriptions, while potentially useful, have no immediate
application and are essentially an exercise in completeness.
ELECTION OF OFFICERS FOR 2002-2003:
Stephen Peters opened the floor for nominations for each of the six
officer positions starting with Chair, Vice-Chair, Secretary, Webmaster,
Postmaster, and Model Librarian. No nominations from the floor were
made. Bob Ross moved that the slate of nominees as read below be elected.
Arpad Muranyi seconded, and the following officers for 2003-2004 were
elected unanimously.
Michael Mirmak, Chair
Lynne Green, Vice Chair
Randy Wolff, Secretary
Syed Huq, Webmaster
John Angulo, Postmaster
Roy Leventhal, Model Librarian
IBIS 4.1 STATUS AND UPDATE
Lynne Green, Cadence Design Systems
Lynne began her presentation by noting that IBIS 4.0 was approved in July,
2002 and a parser is expected in the third quarter of 2003. IBIS 4.1 will
include five additional BIRDs, including the major addition of multi-lingual
modeling support. Lynne also noted that there is one outstanding BIRD
that will probably not be included in IBIS 4.1.
The remaining BIRDS to be included in IBIS 4.1 address several different
issues. Improved support for differential buffers is addressed through
BIRD 77. BIRD 80 added ext_ref as a new [Pin Mapping] column, helping to
drive adoption of BIRD 78 to extend the line length limit to 120 characters.
Finally, BIRD 81 clarifies [Series Pin Mapping] and series model usage.
The next step in IBIS specification development is presentation of
the draft version of IBIS 4.1 to the Open Forum for an approval vote.
Once the specification is approved, a parser is written and any issues
which arise from parser development are folded into IBIS
4.2 (which may include an EMC specification as defined by BIRD 74).
When the IBIS 4.2 parser is stable, the specification will be presented
to ANSI/EIA for approval through a formal letter ballot.
BEHAVIORAL VHDL-AMS I/O BUFFER MODELS USING IBIS
Arpad Muranyi, Intel Corp. and Luca Giacotto, Université Joseph Fourier
Arpad stated that the motivation for the presentation was to develop
algorithms for simulating a basic I/O buffer model IBIS description
using VHDL-AMS. Source code for this effort will be made freely available
to anyone interested. Arpad noted that his presentation was not
intended as a tutorial on the VHDL-AMS language.
Arpad first presented a standard IBIS I/O model with four IV curves
(pullup, pulldown, clamps) and Vt tables that describe switching.
Arpad then introduced the classic equations which define the Vt and
IV curve relationship, where the IV curves scale the Vt curves through
coefficients called K factors (here, Kpu and Kpd for the pullup and
pulldown factors, respectively). Arpad noted that Kpu and Kpd are assumed
to be identical which may not be accurate in all cases.
Arpad then went on to show the equations as implemented in VHDL-AMS code,
where the two equations are solved to find the value of K. The equations
are placed into a for loop, and K is resolved for each point on the pullup
or pulldown curve. Arpad noted that the K values are calculated and stored
from the model data when the simulator is initialized, not at run time.
Arpad showed results comparing HSPICE B-element and AMS implementation
results to data from the source transistor model. In general, the B-element
and AMS curves matched closely, but were not identical.
Luca then presented a slightly different version of the code with
separate structures defining the pullup, pulldown and clamp behaviors.
The top-level code contained only the concurrent statements of the digital
logic and transistors.
Luca then went on to explain how to solve an existing problem first noted
when creating models for DDR memory interfaces. These models connect
their terminations to VCC/2 when used, but the model is extracted with
fixture voltages of VCC and GND. The best approach to using this data
in these cases is that, while some simulators can only use two Vt tables
at a time, different sets of Vt tables may be used at different times or
depending on the model's initial conditions. Luca described a four-curve
data set, with fixture voltages set to 0, 1/3*Vcc, 2/3*Vcc and Vcc. With
this set of waveforms, the AMS implementation overlays transistor level
model results across the entire run time. Luca noted that this approach
still assumes that all Vt tables have the same R_fixture, which generally
matches the target system impedance.
A discussion followed regarding loading where Al Davis and others noted
that lower impedance loads will cause more error than higher impedance
loads for a given set of model data.
Arpad's and Luca's files will be uploaded to the IBIS web site.
IBIS ALGORITHMS REVISITED
Bob Ross, Teraspeed
Bob stated that his slides were part of a larger presentation given
at the IEEE SPI Conference in Siena, Italy earlier this year. Bob noted
that, early on, IBIS tools settled on a data-processing algorithm
involving two waveforms, but there are other algorithms possible. These
include using multiple tables with dynamic interpolation and modeling the
transistors themselves as was done for the Japanese IMIC specification.
Recently radial base functions have also been considered.
Bob first explained a very simple algorithm using only ramp data and
assuming a 5 volt linear device driving into a 50 ohm resistive load.
Additional variations, including Norton and Thevenin linear transitions
plus table multipliers were addressed, with a comparison to actual
waveforms. Bob showed how two waveforms were required to get independent K
values for IBIS pullup and pulldown data.
More advanced simulation techniques must handle generalized loading cases,
rather than loads which are purely resistive. Bob used a SPICE netlist to
address the problem, incorporating two models in a feedback loop of an
operational amplifier, where the amplifier itself drove the scaling or K
table values. The input of the amplifier, being connected to output node,
would then converge on an appropriate solution for the load used.
Finally, Bob addressed overclocking IBIS buffers, where IBIS models are
driven in simulation over shorter periods than allowed by the length
of the Vt waveforms. Unfortunately, no immediate solution to this
problem is currently available. A discussion followed the presentation,
in which Al Davis, Arpad Muranyi and Bob examined additional alternatives
for addressing overclocking and buffer characterization.
AD-HOC PRESENTATION ON HOW TO MODEL THE SWITCHING INTO AN UNFINISHED
EDGE PROBLEM (Ad Hoc)
Arpad Muranyi, Intel Corp.
In addition to his scheduled presentations, Arpad provided an ad-hoc
set of slides addressing the driver overclocking problem. Using several
image overlays, Arpad demonstrated that overclocked buffers show a
relatively constant delay between pulldown turning off and pullup
turning on, and vice-versa. Arpad proposed that this delay could be
characterized and included with other IBIS data as a parameter.
MODELING ON-DIE TERMINATIONS
Arpad Muranyi, Intel Corp.
Arpad began his presentation by noting some of the more advanced
design features now commonly available, including dynamic clamps,
staged buffers, kicker circuits and the like. While many of these
features may be difficult to model without intimate knowledge of the
buffer design, a general rule of thumb is that any design aspect
which is static should be represented through the IBIS clamp tables.
Users and model makers observing this rule for terminations should
be careful to use the appropriate rail for correct power and ground
bounce simulations. Most especially, double counting of these
termination features should be avoided whenever possible.
Arpad classified the types of termination as series, parallel or
switched parallel. Series termination does not require any special
analysis for inclusion in IBIS as it will naturally be included in
the IV curve shapes. Parallel termination behaviors should be placed
in clamp tables by sweeping the voltage on the pad from -Vcc to
2*Vcc, both using ground referencing and Vcc referencing. By
finding the curve which passes through the origin, one can find
the curve set most appropriate in which to include the resistor. This
curve will be cut at Vcc, while the other will be cut at ground. The curve
without the resistor can then be normalized or shifted to pass through
the IV origin. Both curves can then be extrapolated to 2*Vcc.
Switch parallel terminations are commonly implemented by leaving either
the pullup or pulldown active when the device receives. In this case,
normal I/O IV curves may be created and the appropriate pullup or
pulldown curve may be copied to a [Submodel] and renamed to be a
dynamic, non-driving clamp. Example IBIS text for this implementation
was provided.
Finally, Arpad addressed the case where both pullup and pulldown
terminations are present in a design. The model maker in this case cannot
be sure how to determine the value of each termination separately when
only the Thevinen equivalent can be observed. Lynne Green and
Bob Ross suggested that analysis of the slopes can be used to
help determine where non-linear resistive termination data can be
included.
OTHER DISCUSSIONS AND AD HOC PRESENTATIONS
Stephen reminded participants that, if they intend to attend DesignCon
East, they should register as soon as possible.
Lynne Green gave a brief report on her observations from the DAC floor.
She noted that a greater number of I/O companies have heard of
IBIS than in previous years, with an increased interest in membership.
I/O companies and organizations expressed general interest in AMS
technologies for mixed electrical and mechanical simulations, but not
necessarily for modeling I/O buffers. Buffer modeling using AMS
is likely to become more prevalent within the next two to three years.
Lynne also mentioned that several tools displayed on the DAC floor
included support of SPICE, AMS and IBIS together. Arpad noted that he
would like to see more AMS implementations with greater model development
and debugging capabilities.
CONCLUDING ITEMS
Stephen Peters thanked the presenters for the great and informative
presentations. After reminding the participants regarding the next
teleconference meeting, Stephen closed the IBIS Summit Meeting.
NEXT MEETING(S):
The next Open Forum meeting will be the IBIS Summit at DesignCon East
on Monday, June 23, 2003. Teleconference bridge details will be
distributed separately.
The Open Forum will also hold a meeting on Friday, June 27, 2003 from
8:00 AM to 10:00 AM Pacific time. A vote on BIRD 74.4 is planned.
============================================================================
NOTES
IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046
michael.mirmak@intel.com
Senior Analog Engineer, Intel Corporation
M/S FM6-45
1900 Prairie City Rd.
Folsom, CA 95630
VICE CHAIR: Lynne Green (425) 788-0412, Fax (425) 451-1871
lgreen@cadence.com
Senior Modeling Engineer, Cadence Design Systems
320 120th Ave NE, Suite B-103, Bellevue, WA 98005-3016
SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475
rrwolff@micron.com
Simulation Engineer, Micron Technology, Inc.
8000 S. Federal Way
Mail Stop: 1-711
Boise, ID 83707-0006
LIBRARIAN: Roy Leventhal (847) 590-9398
roy.leventhal@ieee.org
Consultant, Leventhal Design and Communications
1924 North Burke Drive
Arlington Heights, Illinois 60004
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008
John_angulo@mentor.com
Development Engineer, Mentor Graphics
14715 N.E. 95th Street, Suite 200
Redmond, WA 98052
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