Subject: RE: [IBIS] Webinar on Differential IBIS Models
From: Muranyi, Arpad (arpad.muranyi@intel.com)
Date: Tue Sep 30 2003 - 16:59:37 PDT
Just to set the records straight, the correct
spelling of my name is: Arpad Muranyi
Thanks,
Arpad
=============================================
-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org]On Behalf Of Lynne
Green
Sent: Tuesday, September 30, 2003 4:43 PM
To: si-list@freelists.org; ibis@eda.org
Subject: [IBIS] Webinar on Differential IBIS Models
Cadence Design Systems presents the next webinar in the IBIS Modeling
series:
Creating Accurate IBIS Models for Differential I/O Buffers
Dr. Lynne Green, Sr. Member Consulting Staff, Cadence Design Systems
Arpad Muryani, Senior Signal Integrity Engineer, Intel Corporation
Wednesday, October 8, 2003 at 10:00-11:00 AM Pacific Time
Design space exploration using signal integrity tools such as
SPECCTRAQuest requires
accurate IBIS models. However, translating SPICE models to IBIS models
has typically
relied on a time-consuming and error-prone process. All too often,
resulting inaccuracies
surfaced late in the design process. This webinar builds on the proven
methodology
presented recently by Dr. Lynne Green in the recent Cadence
SPICE-to-IBIS Modeling
Methodology webinar.
Learn More > http://www.cadencepcb.com/webinar/IBISDiff/learnmore.asp
Register > http://www.cadencepcb.com/webinar/IBISDiff/registration.asp
Archived webinars > http://www.cadencepcb.com/webinar/
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