Dear Mr. Ingraham,
Thanks so much for your kindly answer. You really give me an elaboration about me questions.
About 1, I should ask our chip vendor to fill out the "TBD" values in their specification.
About 3,
A. So, chips are usually not made according to SPICE file; On the contrary, SPICE files are extracted from chip and guess.
Thus, SPICE-derived IBIS model and encrypted SPICE model are not as accurate as measurement-based IBIS model. (except some situation)
B. So, the extremes of SPICE-derived model are only expectations. And only if chip vendor spend a lot of money and a lot of time to screen the extreme chips from manufacture process and then use a long time to measure it, we cannot get a accurate IBIS model. I am afraid that the schedule of IBIS model is too slow to let us prevent SI problems in advance...
C. If everything is optimized, how long will it usually take to generate a IBIS3.2 model of one I/O buffer?
About 4,
A. I would like to know whether the influence from fab process is smaller than the influence from temperature and voltage or not.
i.e. if chip vendors didn't spend their resource to select the typical and extreme chips, how much will the simulation result be influenced?
B. For most IBIS model, the typical temperature is room temperature, however, for some chips (ex: CPU), the temperature is much higher than room temperature.
Is it reasonable to ask chip vendors to change the typical temperature.
Could you also give some comments to the rest two questions if it is conveniet for you? Thank you in advance.
Best regards
Andrew Chien
-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org]On Behalf Of Andrew Ingraham
Sent: Thursday, December 30, 2004 12:08 AM
To: ibis@eda.org; ibis-users@eda.org
Subject: [IBIS] Re: Basic questions about IBIS
> I know that we can obtain the delay difference between "test load" and
> "trace", but I don't know whether it is possible to ask chip vendors to
> provide the "gate delay + test load" of each signal.
For chip outputs, gate delays should always be specified with the test load.
That's the purpose of the test load. Check the data sheet; it should say
somewhere that output delays are specified with the load.
> 2. What item is the main purpose of signal integrity simulation works?
> Overshoot, ringback, transition time, or crosstalk?
Yes! To all, and more. :-)
I would not try to say which one of these is most important, because it
depends on the situation.
> 3. Is measurement-based IBIS model more accurate that SPICE
> simulation-based IBIS model?
That depends.
Obviously, a measurement-based model can accurately represent (one sample
of a) real device. The SPICE model might or might not bear much similarity
to reality. If not, then clearly the measurement-based model can be better.
It depends on the care that went into making the SPICE model, whether they
bothered to correlate it with measurements, etc.
The IBIS model should have min and max characteristics, but they might not
have sample parts of both extremes. Thus, some extrapolation (based on best
guesses) may be required. Of course the same is true of SPICE models too.
Measurement-based models tend to have some "noise" that may need to be
smoothed out. A lot of fine noise in the tables can lead to odd behavior in
the simulator.
Many SPICE models are created from expectations of what the chip vendor
thinks he ought to get from his new process, and the targets can be wrong.
Plus, oftentimes there are difficulties extracting SPICE models from certain
structures (particularly in the I/O area), and it is easy to get a lousy
SPICE model; one that's totally missing the clamp devices, or has the wrong
drive strength, or whatever.
Depending on the frequencies of interest, it can take a lot of skill to
correctly measure and model the characteristics of the device. This is one
area where a SPICE-derived model may have the advantage (assuming, of
course, that the SPICE model was good at those frequencies).
> One of our chip vendor said it, and we do obtain more accurate results
> from measurement-based IBIS model. However, they said that it takes 3-4
> months to generate a measurement-based IBIS model, so they are not willing
> to generate the IBIS model of the other I/O buffers on the same device for
> us.
> Is it possible to generate an accurate enough IBIS model in a short
> time?
Yes.
The 3-4 months includes the time to schedule the work, assign personnel and
equipment, get up to speed, some padding in case something goes wrong and
they need to start over, write up reports, etc. They probably don't have
someone sitting around with nothing to do who can start on your devices
today. Hence the extra time.
> 4. When we want to generate a measurement-based IBIS model How can we
> select the max, min, typ buffer strength chip?
You can adjust the supply voltages and perhaps the temperature when making
these measurements, but there's nothing YOU can do to represent a best-case
or worst-case chip from the fab. The IC manufacturer can do this, but it's
not cheap.
Either you get samples that are certified by the vendor to represent the
likely extremes of the fab process, or you take samples, hope that they are
typical, and margin the curves by some amount.
Regards,
Andy
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Received on Wed Dec 29 23:18:01 2004
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