Zhiping,
I would like to comment on your paragraph on the gate modulation
effect. I think your statement "For the current IBIS, the power
is assumed to be perfect" is not entirely true. Think about the
"Vcc relative" IV curves and the package modeling, for example.
The origin of each IV curve is associated with a corresponding
[XYZ Reference] keyword. Using appropriate package parasitics and
[Pin Mapping], these reference voltages are allowed to bounce as
the buffers are switching. So the power of the buffers do not
have to be perfect in the IBIS world.
It is a different story that the strength of the buffer is not
modulated in most IBIS simulators based on the bouncing rail
voltages. But this capability would not be very difficult to
add. We could get started by just adding two parameters to
the IBIS specification which would have the same meaning that
I mentioned before in the HSPICE B-element.
The first thing to decide is whether these should be part of
BIRD95. If yes, we can continue on this thread and discuss
how it should be defined. If not, we can start another thread
and BIRD to do it separately. Any takers to write it up?
Arpad
=================================================================
-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Zhiping Yang
Sent: Wednesday, January 05, 2005 3:30 PM
To: Roy Leventhal; twesterh@cisco.com; ibis@eda.org; 'ibis-users'
Subject: [IBIS-Users] Re: [IBIS] RE: BIRD95: Power Integrity Analysis Using IBIS
Hi Roy,
Very well said about the IBIS model.
For current BIRD95, our intention was not to completely solving the power
integrity problem in one proposal. As a first step to improve the IBIS
model capability and accuracy in SSO simulation, we proposed to add IvsT
information of the I/O power pin into existing IBIS model. We think this
IvsT table will provide enough info on Xbar current, Pre-driver current from
VDDQ, internal termination current and embedded decoupling current within
I/O cell which are neglected in current IBIS model. We really not expect
IBIS model with added IvsT info could complete replace the SPICE model in
SSO simulation, but we do think it can greatly reduce the simulation
accuracy gap between the SPICE model and IBIS model.
About the "gate modulation effect" Arpad and Todd mentioned, I think it is
more like a problem which can be correctly addressed by EDA tool vendor.
Certainly in order to correctly solve this problem in IBIS, the IBIS model
should provide enough information for the EDA tool vendor to use them. For
the current IBIS, the power is assumed to be perfect, so there is no correct
way to consider this effect in the EDA tool. With the introduction of
BIRD95, EDA tool vendors could think how to simulate power noise due to I/O
switching (as a first step, the mutual impact between the I/O network and
power network may not be able to fully considered). I think it is
relatively easily to implement the impact of I/O noise to the power network,
but it is relatively hard to implement the impact of power noise to the I/O
network by using IBIS model. I may be wrong. There are a lot of smart
people in the EDA industry and they may be able to figure out how to
implement it correctly (or closer to the SPICE model).
Best regards,
Zhiping
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Received on Wed Jan 5 16:03:52 2005
This archive was generated by hypermail 2.1.8 : Wed Jan 05 2005 - 16:06:34 PST