[IBIS] BIRD 95.2 on-die decap

Syed,

At today's teleconference, I tried to clarify the suggestion I made for
BIRD 95.2 yesterday.  The BIRD does not explicitly state that it is not
intended for modeling the I/O power distribution network on-die.  The
actual intent is to document the power node currents and provide an
impedance model for the power nodes of the transistor-level buffer
model.  The goal, as Todd Westerhoff put it, is to substitute an IBIS
behavioral description for the transistor-level buffer subcircuit inside
whatever power distribution and packaging network you have available.
However, the description for the C_p+b, ESR and ESL elements in the
second diagram:

|                 C_p+b    - Bypass + Parasitic Capacitance
|                 ESR      - Equivalent Series Resistance for on-die
Decap
|                 ESL      - Equivalent Series Inductance for on-die
Decap

and the presence of these elements apart from the pre-driver circuit
might make it hard for a lot of readers to appreciate that these
elements are a behavioral model of the decoupling within the driver and
pre-driver.

Surely, for accurate SSO simulation, we will sometimes have to consider
the additional decoupling in the on-die power distribution network.  The
decoupling here is shared among multiple buffers, and of course it would
not make sense to embed it into ZVDDQ elements, which are meant to be
replicated at every instance of the buffer, i.e. "scaled" with the size
of the SSO simulation.  You already made this point in slide 7 of your
DesignCon presentation with Vinu and Zhiping.  My suggestion is to make
this distinction between what we're doing in BIRD 95 and what we leave
to other BIRD's or techniques more explicit in the text.

Thanks,

John Angulo
Software Development Engineer
Hyperlynx Products
Mentor Graphics Corp.

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