Re: [IBIS] Error in spice simulation

Hi Sanjay,

 Here is what i feel can solve your problems,

1)rux1.out: **error**  internal timestep too small in transient analysis

In ramp up data for the fast process i.e rux1.out the .tran statement has an internal time step lower than required.This might happen because of the rise time/fall time of pulse applied to generate the data has time lower than time step applied to .tran statement.
So if you increase the time step of the .tran statement.If that solves the problem its fine.

Sometimes even in that case you may find the dv/dt as negative in .ibs file for the buffer.Then change the sim time in *.s2i file and give the runs again.

2) rut1.st0: **error**  no dc path to ground from node        0:en2n             defined in

 In this case check the definitions in the subckt call given from the *.sp file written before giving the s2ibis run.
 So ground e2n signal or set it high depending on functionality of buffer.

If thats a bidirectional buffer then [enable] needs to be dealt with in the *.s2i file

Hope this helps

regards
arnab hazarika




  ----- Original Message ----- 
  From: sanjay.bobe@wipro.com 
  To: ibis@eda.org 
  Sent: Friday, March 18, 2005 1:04 AM
  Subject: [IBIS] Error in spice simulation


  Hi,

  While generating IO I-V tables from spice netlist, using hspice 2004.09, I am getting following error.

  rut1.st0: **error**  no dc path to ground from node        0:en2n             defined in
  rux1.out: **error**  internal timestep too small in transient analysis

  What could be the problem? Is this related to simulation time?

  Thanks and regards
  Sanjay Bobe



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