[IBIS] RE: [IBIS-Users] delay problem

Hi, Ambrish,

 

a)       IBIS simulators trigger with a signal having a finite slope, and
buffer toggles at some voltage on that slope, so a small time offset is not
unusual.  I would be more concerned about why the two waveform shapes are
different, esp. at the top and bottom of the transitions.

b)       The timing information is in the V-t tables.  These include the
buffer's internal delay, as well as timing differences between rising and
falling transitions (relative to the buffer's "signal" toggle.

c)       All delay effects internal to the buffer are important. Later,
system timing can adjust simulated delays relative to the data sheet using
the standard load (Vmeas, etc.).  This relies on V-t tables being correct.

 

Please feel free to send a sample model to the IBIS Model Review Committee.
We want to support your efforts on s2ibis3.

 

Best regards,

Lynne

 

  _____  

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of Ambrish Varma
Sent: Tuesday, April 05, 2005 4:00 PM
To: ibis-users@eda.org
Cc: ibis@eda.org
Subject: [IBIS-Users] delay problem

 

Hello,

I know this problem has been asked several times and answered several times
as well.

So my apologies in advance.

 

Attached is a comparison of hspice and ibis circuits. I want to know 

a)       Why there is a delay at the falling edge.

b)       Where delay information is stored in an IBIS model, if at all.

c)       Does it matter to have a delay? The periods seem to match up.

The IBIS model is created from hspice netlist.

 

Thanks for any feedback,

Regards, 

Ambrish.

 

Ambrish K Varma

akvarma@ncsu.edu

North Carolina State University

ph(919)513-2015, fax(919)515-2285

 




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