RE: [IBIS] [Composite Current] with series termination

Mike raised a very interesting and good question.  If I may
rephrase it, this is what he asked:

Since the output and supply current profile is also effected 
by the length of the transmission line, are the I(t) tables
of BIRD95 going to work in practice when people will use the
buffer model with all kinds of transmission line lengths?

My hand waving answer to this is as follows.  The reason I am
saying hand waving is because I didn't test this, so I can't
tell for sure.

The I(t) tables seem to describe only those "extra" currents
which are happening when the buffer is switching.  (Crow bar,
pre-driver noise, etc...).  This is not longer than the length
of the Vt curves in duration.  After the buffer is done switching,
the currents are completely determined by the IV curve and the
voltage on the pad.  Therefore, since the buffer is in the
"steady state" when the reflection comes back from the end
of the T-line, it shouldn't really matter when that happens.

Is my thinking correct?  Could anyone try this (Sam, Zhiping)
to prove it?

Thanks,

Arpad
===================================================================


-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Zhiping Yang (zhiping)
Sent: Thursday, October 13, 2005 2:05 PM
To: Mike LaBonte (milabont); ibis@eda.org
Subject: RE: [IBIS] [Composite Current] with series termination

Hi Mike,

I might not understand your questions completely.   Here is what I can
think about it.

First, the composite current will be specified only under certain load
conditions and it is the total current.  In the integration of composite
current into IBIS implementation, it is not simple addition of composite
current to IBIS model, it has to be pre-processed and the added current
will be the difference between composite current and pure IBIS model
current.  

For the case you specified, the BIRD95 will improve the accuracy at the
rising/falling edge.  The constant 25mA current after rising/falling
edge should be able to taking care by existing IBIS simulator.

Please call me if you still have any further questions.  Thanks.

Best regards,

Zhiping

 

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Mike
LaBonte (milabont)
Sent: Thursday, October 13, 2005 10:25 AM
To: ibis@eda.org
Subject: [IBIS] [Composite Current] with series termination

I would like to ask the simulator gurus out there how the BIRD95
[Composite Current] waveform would be used with series termination, ie.
reflective switching. With a 2.5V series terminated 0.5ns buffer
driving, say, a 2ns, 50 ohm transmission line, the pad voltage rises to
1.25V, stays there for quite a while, then completes the rise to 2.5V.
During the 1.25V period the pad current will be flat at about 1.25/50 =
25mA. This pad current flattening begins about half way through the
"normal" rise time, as measured using the standard test fixtures. At
that point the pad current flattens out at 25mA, but the [Composite
Current] is telling the simulator the VDDQ current needs to continue
dropping to zero.

Here are the 3 currents I see in a rising edge simulation of such a test
fixture. Sorry, I can't make the 3 curves add up to zero at all points
using ASCII graphics:

Pad current  :

-50 ---                                  reflection back to driver here
                                                     |

                                                     v

            _______________________________________/\

           /                                         \

          /                                           \

  0 ___  /                                             \_____________

 


VDDQ current  :

          /\
50 ---   | |                                                    
         | |

         | |

         | \_______________________________________/\

         |                                           \

         |                                            \

  0 ___  /                                             \_____________



GND current  :

              
-50 ---                                                         
          /\

         | |

         | |

         | |

         | |

  0 ___  /  \_______________________________________/\_______________



[Composite Current] probably looks like this  :

          /\
50 ---   | |                                                    
         | |

         | |

         | |

         | |

         | |

  0 ___  /  \________________________________________________________   
      

My question is, will the simulator deliver the constant 25mA current at
the pad for several nanoseconds if it is being told that VDDQ current is
a spike that drops to zero at the end of the 0.5ns "normal" rise time?
This may have come up before, but if so I haven't heard it put quite
this way.

Mike LaBonte

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