[IBIS] Open drain strange behaviour

Hello everybody

  I 'd like to have some information about a strange behaviour of Open 
drain buffer
  Ibis model. I have noticed a mismatch between Transistor level and 
Ibis model
  voltage output during a transient analysis. In fact in presence of the 
same input voltage
  wave and the same value of load resistance (for example 70 ohm),
  we can observe a delay between TL output and Ibis output. This delay 
is the same
  if we change the value of  load resistance. What is the cause of this 
strange behaviour?

  Thanks and best regards

        Roberto Izzi

 
 


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