[IBIS] Question on IBIS Quality Spec Interpretation (section 4.4.2)

 

One of our development groups is currently reviewing one of our new IBIS
models for LEVEL 0 compliance prior to initial issue to customers. A
question has come up regarding the interpretation of section 4.4.2 in
the iq_specification.txt document (IBIS QUALITY SPECIFICATION - Revision
1.0).

 

 

While the text of the document defines the intent very precisely, can
someone please provide an interpretation of what really needs to be
checked?

 

Initially the group thought it was as simple as verifying that the
voltages at the endoints of the V-T table were within 2% of the endpoint
voltages in the I-V tables, but after re-reading section 4.4.2 we are
not convinced that is a correct interpretation.

 

 

 

4.4.2  {LEVEL 0}  V-T table endpoints consistent with I-V tables

 

  The voltage associated with the intersection of the V_fixture,
R_fixture,

  and R_dut (if present) load line with the respective combined high/low

  DC I-V characteristic should be within 2% of the V-T table DC
endpoints

  based on the V-T table DC range.

 

  The combined High State DC I-V characteristic is defined as the sum

  of the [Power Clamp], [GND Clamp], and [Pullup] I-V tables (ground

  relative). Similarly, the combined Low State DC I-V characteristic is

  defined as the sum of the [Power Clamp], [GND clamp], and [Pulldown]

  I-V tables (ground relative).

 

 

 

-Ray Anderson

 

Raymond Anderson

Senior Signal Integrity Staff Engineer

Product Technology Department

Advanced Package R&D

Xilinx Inc.

 

 



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