RE: [IBIS] More Details about Vinh+, Vinh-, Vinl+, Vinl- (clarification)

From: Mike LaBonte \(milabont\) <milabont_at_.....>
Date: Thu Sep 21 2006 - 06:00:37 PDT
The vinh-/vinh+/vinl-/vinl+ parameters should be used only if your
device has hysteresis designed in, like Schmitt trigger devices. An
example Schmitt trigger datasheet can be found at 
http://focus.ti.com/lit/ds/symlink/cd40106b.pdf . In that data sheet
there are min and max values for Vp, and for Vn. The JEDEC specification
http://www.jedec.org/download/search/jesd8-5A.pdf may help too.
 
MIke

________________________________

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of
Sudarshan Honnudike
Sent: Tuesday, September 19, 2006 10:15 AM
To: Sudarshan Honnudike
Cc: ibis@eda-stds.org; Mirmak, Michael; owner-ibis@eda.org
Subject: RE: [IBIS] More Details about Vinh+, Vinh-, Vinl+, Vinl-
(clarification)



Hello All, 

As I am not getting any IBIS mails from past 4 to 5 days I doubt there
might be some problem with my mailing account. 
Can anybody give answers to the questions I asked below by replying to
this mail and also to another 
email id :  hn_sudarshan@yahoo.com . 

FYI.. 

I hope I will get response this time. 

Thanks in advance. 

Best Regards,

Sudarshan HN
CTO /Process & Library Technology
NXP Semiconductors
Banglore-08
Ph:080-25579000  Extn:1586
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@philips.com 








Sudarshan Honnudike 

Sent by: 
owner-ibis@server.eda.org 

2006-09-18 11:30 AM 

To
Sudarshan Honnudike/BTC/SC/PHILIPS@PHILIPS 
cc
ibis@server.eda-stds.org
"Mirmak, Michael" <michael.mirmak@intel.com>
owner-ibis@server.eda.org 
Subject
RE: [IBIS] More Details about Vinh+, Vinh-, Vinl+, Vinl-
(clarification) 
Classification

	





Hello All, 

Can anybody reply to my message that I have sent few days back. I need a
urgent reply. 

FYI.. 

Thanks. 

Best Regards,

Sudarshan HN
CTO /Process & Library Technology
NXP Semiconductors
Banglore-08
Ph:080-25579000  Extn:1586
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@philips.com 







Sudarshan Honnudike 

Sent by: 
owner-ibis@server.eda.org 

2006-09-14 11:37 AM 



To
"Mirmak, Michael" <michael.mirmak@intel.com> 
cc
ibis@server.eda-stds.org 
Subject
RE: [IBIS] More Details about Vinh+, Vinh-, Vinl+, Vinl-
(clarification) 
Classification


	






Hi Michael, 

Thanks for the detailed explanation. 

Actually I was aware of your explanation that you have explained in the
first three paragraphs. I wanted more 
explanation for the fourth paragraph that you have written. 

I am really not convinced about the two thresholds they define( Vinh+
and Vinh- for rising waveform and Vinl+ & Vinl- 
for falling waveform). 

      What we normally do is , to apply a rising waveform and measure
the input voltage at which output switches from low to high. 
So this gives Vinh and apply a falling waveform and measure the input
voltage at which output switched from high to low.So this gives Vinl. 

 
So where is the question of two thresholds there ? At one point it
switches. 

What I understand from these definitions after discussing with the
designers is, these parameters define the hysteresis parameters 
over the variation in temperature and process. Measure the Vinh and Vinl
over best, typical and worst case corners by varying 
the temperature and process and keeping the voltage constant. 

I just tried doing simulations in the way I said above and these are the
results I got for one cell. 
                      Typical                 Best
Worst 

Vinh                        0.864                        0.878
0.828 

Vinl                        0.846                        0.873
0.792 


So take two values from Vinh which gives Vinh+ and Vinh- and take two
values from Vinl which gives Vinl+ and Vinl-. 

From the above example we can write 

Vinh+                0.878 
Vinh-                0.828 
Vinl+                0.873 
Vinl-                0.792 

I dont know what I have understood is correct or not. Please correct me
if I am wrong by giving necessary explanation. 

Thanks. 

Best Regards,

Sudarshan HN
CTO /Process & Library Technology
NXP Semiconductors
Banglore-08
Ph:080-25579000  Extn:1586
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@philips.com 






"Mirmak, Michael" <michael.mirmak@intel.com> 

2006-09-12 09:44 PM 



To
<ibis@server.eda-stds.org>
Sudarshan Honnudike/BTC/SC/PHILIPS@PHILIPS 
cc
Subject
RE: [IBIS] More Details about Vinh+, Vinh-, Vinl+, Vinl-
(clarification) 
Classification




	






To clarify, I did not enclose a drawing in my original e-mail -- my last
sentences were referring to the specification document itself.  An
explanation of hysteresis and a drawing of a sample waveform are
available in the IBIS 4.2 specification, on pages 37 and 38 of the PDF
version.   

The PDF is available at http://www.eda-stds.org/ibis/ver4.2/
<http://www.eda-stds.org/ibis/ver4.2/> . 

- Michael Mirmak 
Intel Corp. 
Chair, EIA IBIS Open Forum 


________________________________

From: Mirmak, Michael 
Sent: Monday, September 11, 2006 14:41
To: 'ibis@server.eda-stds.org'; 'sudarshan.honnudike@philips.com'
Subject: RE: [IBIS] More Details about Vinh+, Vinh-, Vinl+, Vinl-

Sudarshan, 

Thanks for your interest in IBIS.  The hysteresis thresholds here are
not directly related to PVT variations any more than normal Vinh and
Vinl thresholds are.  The difference for these thresholds is that they
are used for receiver designs which support hysteresis or bistable
latching of logic levels based on input signals. 

For example, LVTTL recognizes 0.8 V as Vinl and 2.0 V as Vinh. Signals
below Vinl are definitively "low" while those above Vinh are
definitively "high," as these represent the guaranteed outer limits of
logic switching by the buffer design.  An individual buffer may have its
actual switching threshold in-between these levels, so a signal that is
seen as "low" for a voltage between these levels for one buffer may not
be seen as "low" for another buffer of the same design, due to
variations.  The outer limits set the guaranteed levels, and so are used
for worst-case timing and SI evaluation. 

A receiver that exhibits hysteresis, on the other hand, might not switch
using the same threshold voltage for input signals going low-to-high
versus those going high-to-low.  An incoming signal which is rising may
therefore cause the hysteresis buffer to switch its output at a voltage
higher than that used for an incoming signal which is falling. 

In the case of the IBIS usage rules, the specification clearly states
that Vinh+ and Vinh- are to be used for low-to-high transitions, while
Vinl+ and Vinl- are to be used for high-to-low transitions.  A drawing
is included for reference. 

I hope this helps... 

- Michael Mirmak 
Intel Corp. 
Chair, EIA IBIS Open Forum 


________________________________

From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On
Behalf Of Sudarshan Honnudike
Sent: Monday, September 11, 2006 04:43
To: ibis@server.eda-stds.org
Subject: [IBIS] More Details about Vinh+, Vinh-, Vinl+, Vinl-


Hello Experts, 

I referred some of the IBIS documents regarding the explanation for
Vinh+, Vinh-, Vinl+, Vinl-. 
But what I got was, 

| Vinh+                         Hysteresis threshold high max Vt+ 
| Vinh-                         Hysteresis threshold high min Vt+ 
| Vinl+                         Hysteresis threshold low max Vt- 
| Vinl-                         Hysteresis threshold low min Vt- 

From the cookbook I came to know that "these parameters are used for
defining two thresholds for the rising edges and 
two thresholds for falling edges ". 

     But I didn't understand what "2 thresholds " mean. Is it something
related to PVT variations (Vinh at fast corner and Vinh at slow corner
)? 

Please let  me know the exact meaning of these parameters as soon as
possible. 

Thanks ! 

Best Regards,

Sudarshan HN
CTO /Process & Library Technology
NXP Semiconductors
Banglore-08
Ph:080-25579000  Extn:1586
seri:sudarsha@inpsblr
E-mail: sudarshan.honnudike@philips.com 



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Received on Thu, 21 Sep 2006 09:00:37 -0400

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