RE: [IBIS] Ibis open drain strange behaviour

Radovan,

I believe the qualifications to time correlation between HSpice and IBIS are
- not necessarily, and yes, if.

Time 0 is an IBIS simulation is not guaranteed to have any special
significance.  You'd like to think that you could simulate your transistor
and IBIS model side by side into the same load and expect them to line up,
but there is no part of the spec that guarantees this.  The IBIS waveform
and the HSpice waveform will match in rise/fall time and shape, but they are
not guaranteed to align in time. 

Time 0 is an IBIS model is arbitrary, which is one of the reasons why
"buffer delay" simulations are used to normalize the simulated interconnect
delays (flight times) to the component timing specifications - this is where
Vref, Rref and Cref come from.

IF the person creating the IBIS model uses a particular ramp rate at the
HSpice model input, and IF the model creator uses the simulated HSpice
waveform in the IBIS model without trimming it, and IF the IBIS simulator
uses a similar ramp rate to stimulate the IBIS model with comparable
triggering thresholds, then - yes, the transistor and IBIS simulations will
line up in time.  In practice, this occurs pretty often - but it's important
to understand why.

Most IBIS extraction software takes the simulated waveform from HSpice and
puts it into the IBIS model unaltered (i.e. the IBIS output waveform does
not start rising at time 0, it includes the "intrinsic" delay of the output
buffer).  As you pointed out, the ramp rate of the input to the buffer (in
both the HSpice and IBIS simulations) is usually very fast compared to the
ramp rate of the output.  Thus, even if the input ramp rates or triggering
thresholds are somewhat mismatched, the difference gets swamped by the much
slower output ramp rate (and the simulations line up, or appear to).  You
need a significant mismatch in the stimulus rates to see a difference.

However, one gets into trouble when the intrinsic delay of the output buffer
approaches the device's data rate.  The output may not finish "switching" in
the IBIS curve before the next data bit is triggered.  This particular
behavior is problematic - the IBIS spec (last I looked) had no specific
recommendation on how simulators should handle "overclocking", and different
simulators handle this different ways.  This is a big problem for
semiconductor suppliers, as their models can have different behavior in
different tools.

The solution?  Well, the IBIS spec does not guarantee that time 0 is when
the input to the output buffer switches.  Time 0 in an IBIS simulation is
arbitrary.  So, the model creators trim the "dead time" off the front end of
the rising and falling V-T curves to ensure the outputs stabilize before the
end of the data unit interval, and the time correlation to HSpice is lost.
There are specific restrictions on how the dead time may be trimmed, which
is a longer discussion.

Point is, time correlation between IBIS and HSpice is not guaranteed.  It
happens frequently, but only as a consequence of the model building process.
Dimitry was correct to point out that time 0 in HSpice is often arbitrary in
itself - if we're dealing with a component with a clock-to-output spec, then
we really have no idea when the output buffer in the device gets triggered
with respect to the device's external clock pin anyway.

Hope that helps, or was at least coherent ...

Todd.

Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite 250
Maynard, MA  01754
(978) 461-0449 x24
twesterh@sisoft.com
www.sisoft.com




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