[IBIS] Re: [IBIS-Users] EBD file syntax

Hi Nam:

I agree with Randy's response that C3 is to ground.

I want to add that the EBD format also has syntax rules to
bring in Series models (such as a series capacitor), if that
is needed for some other configuration.

Bob

rrwolff@micron.com wrote:
> Nam,
>  
> Your syntax looks fine to me.  Capacitor C3 would be to an ideal 
> ground.  In fact, all capacitors are connected to an ideal ground, even 
> in the transmission line case, where the capacitance is part of a 
> transmission line that references ideal ground.
>  
> Regards,
> Randy
>  
> 
> Randy Wolff
> SI Modeling Manager
> Signal Integrity R&D Group
> Micron Technology, Inc.
> 
> 
> ------------------------------------------------------------------------
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On 
> Behalf Of Nguyen, Duynam
> Sent: Wednesday, August 22, 2007 1:25 PM
> To: ibis@eda.org
> Cc: ibis-users@eda.org
> Subject: [IBIS-Users] EBD file syntax
> 
>  
> 
> Dear expert,
> 
> I am trying to describe the following situation in an EBD file: a signal 
> net that goes from a die pad to a package pin A9. Physically, this 
> signal net consists of two traces. Each trace is on a different layer 
> and they are connected together by a via which is modeled as a small 
> capacitor of value c3 to ground. The die
> 
> pad and the package pin are modeled by a series L and a grounded C.
> 
> My EBD file attempt is depicted as follows
> 
>  
> 
> [Path Description] SIGNAL_NAME
> 
> Pin A9
> 
> Len = 0            L = l1 C = c1               /
> 
> Len = length2   L=l2   C = c2    R=r2     /
> 
> Len = 0                     C = c3                /         ç Allowed ?
> 
> Len = length4  L=l4    C = c4    R=r4     /
> 
> Len = 0           L = l5  C = c5                /
> 
> Node DIE.5085      
> 
>  
> 
> I have 2 questions:
> 
> 1. About the representation of the capacitance c3 in the EBD file, do I 
> violate any EBD file specification by doing this ?
> 
>    Assuming the specification allows it, would the capacitance c3 be 
> interpreted as grounded or in-series  ?  
> 
> 2. If the representation of the capacitance c3 as above is not allowed, 
> can I take out the offending line and the rest is still permitted ?
> 
>    In other words, there are still two traces with an electrical 
> discontinuity connecting them as follow:
> 
> [Path Description] SIGNAL_NAME
> 
> Pin A9
> 
> Len = 0            L = l1 C = c1               /
> 
> Len = length2   L=l2   C = c2    R=r2     /
> 
> Len = length4  L=l4    C = c4    R=r4     /
> 
> Len = 0           L = l5  C = c5                /
> 
> Node DIE.5085      
> 
>  
> 
> Thank you much,
> 
> Nam
> 
> 
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-- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Labs
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http://www.teraspeed.com           503-246-8048 Direct
bob@teraspeed.com

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