[IBIS] RE: IBIS model behaviour between Vinh and Vinl input

Akilesh,

A SPICE model does what the device does (more or less).

An IBIS model's Vinh and Vinl does what the input specification
tells you when you look at a SPICE waveform and try to decide
whether the waveform you got was good enough to consider
logic high or logic low.  IBIS does not describe how the
device behaves between Vinh and Vinl.

Arpad
================================================================= 

-----Original Message-----
From: Akhilesh CHANDRA [mailto:akhilesh.chandra@st.com] 
Sent: Thursday, January 03, 2008 4:22 AM
To: ibis@server.eda-stds.org; Muranyi, Arpad;
owner-ibis-users@server.eda.org; ibis-users@server.eda.org
Cc: 'akhilesh chandra'
Subject: IBIS model behaviour between Vinh and Vinl input


 


 Hello Experts,

   I am using IBIS model of hysterics cell. In my model Vinh and Vinl
have
different values as per design specs. When I run it with one of the
simulator then it show output at constant voltage(VDDE/2) between Vinh
and
vinl inputs, while spice show continuous behavior with same simulator so
there is big mismatch between IBIS and spice result.
   Can anyone explain us what IBIS standard say about output behavior
between Vinh and Vinl input values.

Regards
Akhilesh



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