RE: [IBIS-Users] Re: [IBIS] V-T data query

As in most cases it depends.  An ECL differential buffer would only have one
set of waveforms with the termination voltage to Vdd - 2V.  CML would also
have only a rising and falling VT tables to Vdd.  Most LVDS buffer models
that I have seen have rising and falling to 1.25V.  But a differential
buffer with "normal" CMOS outputs would have rising and falling VT tables to
both ground and Vdd.

 

You can find out more about how to model by reading the IBIS cook book.

 

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065

503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827 

 

From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of shantala hegde
Sent: Monday, March 30, 2009 6:40 AM
To: ibis-users@server.eda.org; ibis@server.eda.org
Subject: [IBIS-Users] Re: [IBIS] V-T data query

 

Hi all,

As we know, ibis model will be having two rising and two falling V-T tables.

For differential buffers, (pad and padn) is it different?
Do we need to have only one V-T table with Voltage source connected to VDDS?

If anybody worked on differential buffer, please comment on this.

Thanks in advance,
Shantala

On Tue, Mar 24, 2009 at 11:41 PM, Lynne D. Green <lgreen22@mindspring.com>
wrote:

Hello, Shantala,

 

IBIS captures only the behavior of the buffer.  Since the magnitude of the
ground (and power) bounce depends on the board, it is not part of the IBIS
model.

 

There have been discussions of ways to address model response to varying
Vcc-Gnd-Vee voltages.  You might want to check the BIRDs and summit papers
on the IBIS web site for further information.

 

Regards,

Lynne

 

  _____  

From: shantala hegde [mailto:h.shantala@gmail.com] 
Sent: Tuesday, March 24, 2009 7:00 AM
To: Lynne D. Green
Subject: Re: [IBIS] V-T data query

Thanks Lynne.

I have one more doubt on rising/falling waveforms.I do not know much on
ground bounce.But, whats the main reason for capturing v-t data with voltage
source connected to ground in case of rising and vice-versa.

I saw this rising/falling  mismatch behaviour in pci buffers.

Thanks in advance,
Shantala






On Tue, Mar 24, 2009 at 9:56 AM, Lynne D. Green <lgreen22@mindspring.com>
wrote:

Hello, Shantala,

 

This turn on/off difference is probably designed to minimize crowbar current
and power consumption.

 

IBIS 4.x and 5.x require all V-t tables to have the same "reference" time
(same clock edge).  As Arpad noted, the same end time is not required in the
tables.

 

Lynne

 

 

"IBIS training when you need it, where you need it."

 

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com

 


 

  _____  

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of shantala
hegde 


Sent: Monday, March 23, 2009 6:54 AM

To: ibis-users@eda.org; ibis@eda.org 


Subject: [IBIS] V-T data query

 

Hello all,

I do have one question VT data.
For example if I have an ibis model where [rising] data with voltage source
connected to VDDS is a fast one.But the one which is  connected to ground is
slow rising.

Say ,rising with vdds has 3ns and rising with ground connetced 10ns.

Is this normal scenario or is it mandatory to have approximately same V-T
end point for both rising/falling.

Regards,
Shantala



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