To All:
The IBIS Open Forum is holding an Asian IBIS Summit Meeting on
Tuesday, November 9, 2010 in Shenzhen, China, a major technology
center.
The event is being held at the Four Points by Sheraton, Shenzhen.
Co-sponsors are listed below. Like in previous years, we are
planning for a large number of attendees including several IBIS
experts from the USA.
The titles of 10 presentation are shown below. Several of these
presentations will be given at the other Asian Summits.
Please register to attend.
Two other Asian IBIS Summits follow this event:
Taipei, Taiwan, Friday, November 12, Sherwood Hotel
Tokyo, Japan, Monday, November 15, JEITA headquarters
Bob Ross
Teraspeed Consulting Group
Lance Wang
IO Methodology Inc.
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ASIAN IBIS SUMMIT (CHINA)
SIXTH CALL FOR PARTICIPATION
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http://www.eda.org/pub/ibis/summits/nov10a/announcement_chinese.pdf
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A S I A N I B I S S U M M I T ( C H I N A )
Time/Date: Tuesday, November 9, 2010, 8:00 AM to 5:30 PM
Meeting starts at 9:00 AM
Location: Four Points by Sheraton
5 Guihua Road
Futian Free Trade Zone
Shenzhen, Guangdong 518038
P. R. China
Room: Shenzhen A (Look for signs)
http://www.starwoodhotels.com/fourpoints/property/overview/index.html?propertyID=1
489&
EM=VTY_FP_1489_shenzhen_overview
Content: Presentations and Discussions
Purpose: Solicit and exchange IBIS and interconnect model related
information and ideas.
Primary Sponsor:
Huawei Technologies
Co-sponsors (in alphabetical order):
Agilent Technologies, Ansoft Corporation,
Cadence Design Systems, Cybernet, Intel Corporation,
IO Methodology, Mentor Graphics Corporation,
Signal Integrity Software (SiSoft),
Sigrity, Synopsys, and ZTE Corporation.
Cost: FREE, including refreshments and buffet lunch
Vendors: Some vendors will have information tables outside
the meeting room
Contact us for details regarding sponsorship.
BACKGROUND
We have held five successful meetings in Shenzhen, Shanghai and Beijing.
This year we are meeting again in Shenzhen where many Chinese and
foreign high technology companies operate. These events are archived
along with all our other Summits:
http://www.eda.org/pub/ibis/summits/
Our objective is to reach out internationally to communicate with
the local experts and to learn of regional concerns.
CONFERENCE LANGUAGE
The conference language is English, but we will plan for technical
translations in English and Chinese. So presenters can optionally
deliver in Chinese as long as an English version of the material is
available.
IBIS SUMMIT
This meeting will be conducted as a formal IBIS Summit Meeting.
Presentations will be archived in an electronic format on our
Summits site, and minutes of the meeting will be issued. However,
no formal decisions requiring votes will be planned.
CALL FOR PARTICIPANTS
People involved in IBIS and interconnect model development, EDA
tool development, and digital circuit design are invited to
participate to the Summit meeting. If you plan to participate,
please register using the information below (in English):
Name:
E-mail address:
Company:
Top-level Web Link:
Country:
Telephone:
Comments:
(Such as assistance for the travel requirements at the end)
Send to BOTH:
Bob Ross, Teraspeed Consulting Group bob@teraspeed.com
Lance Wang, IO Methology Inc. lwang@iometh.com
SIGNUP DEADLINE: November 4, 2010
AGENDA
8:15 - 9:00 Vendor table setup and tables
8:30 - 9:00 Sign in
9:00 - 12:00 Presentations
12:00 - 13:30 Free buffet lunch, vendor tables
13:30 - 17:00 Presentations
The specific agenda is being developed. The presentations cover
a range of topics from user experiences, IBIS clarifications, and
future technical directions in IBIS.
Program Titles:
IO Methodology:
Point Reduction Method for IBIS Curves
Sigrity
IBIS for SSO Analysis
Huawei Technologies:
PDN Design and Analysis Methodology in SI&PI Co-design
Micron Technology:
Correlating C_pin Capacitance with Measurements
Agilent Technologies:
Automated AMI Model Generation & Validation
Huawei Technologies and Sigrity:
Spice Sub-circuit Support for Serial Link Channel Design by Using
IBIS [External Model]
Flextronics and Cadence Design Systems:
Extending/Leveraging IBIS Constructs to Model High-Speed I/Os
and Packages using AMI, Spice, and S-Parameters
Intel Corporation:
IBIS-ISS: What Is It and What It Means to You
ZTE Corporation:
Modeling Methods for Complex S-parameters in Touchstone 2.0
Cadence Design Systems, Sigrity, and Fujitsu VLSI Limited:
Model Connection Protocol Extensions for Mixed Signal SiP
LIST OF NEARBY HOTELS AND TRAVEL RULES
Hotels in all price ranges can be found through internet searches.
Comply with your travel rules, such as indicated in the link
below to China and Shenzhen. Work with your travel agent. Notify
us as a sign-up comment if you need assistance. Visas, if needed,
should fall in the visit/business category:
http://travel.state.gov/travel/cis_pa_tw/cis/cis_1089.html
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-- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993Received on Tue Oct 19 14:40:17 2010
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