[IBIS] RE: [IBIS-Users] Multi level IBIS model development (Ethernet)

Hi Vishrant,

Usually when developing an IBIS model that has anything more than standard
output design you will have to look into some of the advanced IBIS keywords
and/or modeling methods. Without fully reviewing the Ethernet 100 BT mode
here are some of your options to model this in IBIS:

. The [Driver Schedule] keyword can be used to model multi-stage
drivers. You model different buffer stages separately and use timing
parameters to dictate final output. Disadvantage here is that there are
limitations on the frequencies you can run the model at depending on how you
setup the timing parameters.

. Everything else really falls into what I call Macro Modeling. You
could try to use the external keyword support for Verilog/VHDL-AMS modeling
but the end model will not be easily supported across all EDA tools. Main
issue here is a lot of the PCB Signal Integrity tools don't have native
support for *AMS models.

There are probably other ways to try and model your design but those are the
ones that I can think of off the top of my head.

Best,

Tim

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of Vishrant GOYAL
Sent: Wednesday, April 27, 2011 6:42 AM
To: ibis-users@eda.org; ibis@eda.org
Subject: [IBIS-Users] Multi level IBIS model development (Ethernet)

Hello Expert,

I am trying to develop ibis model for Ethernet Phy for 100 BT mode.

In 100 BT mode there are 3 level possible at the output (TXP and TXN).

Means for every 1's at the input data, output will switch between three
levels

and for every 0's output will remain on the same level.

So for given below input data stream we got following output from the driver
(Similar but opposite output on TXN)

0 1 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 (Input DATA)

 vcm

- How could I develop the ibis for Multi level signals?

Can anyone give some light on this model development.

Thanks & Regards,

Vishrant Goyal

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