To All:
The IBIS Open Forum is holding its second Asian IBIS Summit Meeting in
Taipei, Taiwan a major technology center, on Monday, November 21, 2011.
Several companies listed below are co-sponsoring this major event at
the Sherwood Hotel, Taipei.
The program titles are listed in the AGENDA section below, and the
actual agenda will be issued later. With well over 140 people
registered, signup is near capacity.
For travel planning, we are also scheduling these Asian IBIS Summit
meetings:
Shanghai, P.R. China, Tuesday November 15, Parkyard Hotel
Yokohama, Japan, Friday, November 18, Pacifico Yokohama
Bob Ross
Teraspeed Consulting Group
Polin Chi
Sigrity
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ASIAN IBIS SUMMIT (TAIPEI)
FIFTH CALL FOR PRESENTATIONS
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A S I A N I B I S S U M M I T ( T A I P E I )
Time/Date: Monday, November 21, 2011, 8:00 AM to 4:30 PM
Meeting starts at 8:30 AM
Location: Sherwood Hotel
11 Min Sheng E Road, Sec. 3
Taipei, Taiwan
Rooms: Ballroom I and II
Content: Presentations and Discussions
Purpose: Solicit and exchange IBIS and interconnect model related
information and ideas.
Co-sponsors (in alphabetical order):
Avant Technology (IO Methodology)
Cadence Design Systems
Foxconn
Intel Corporation
Sigrity
Synopsys
Cost: FREE, including refreshments and buffet lunch
Vendors: Some vendors will have information tables outside the
meeting room
Contact us for details regarding sponsorship.
BACKGROUND
We have held many successful Summit meetings in Asia in the past
six years. This meeting will be our second in Taipei where many
national and international high technology companies operate.
Our objective is to reach out internationally to communicate with
the local experts and to learn of regional concerns.
CONFERENCE LANGUAGE
The conference language is English, but we will plan for technical
translations in English and Chinese. So presenters can optionally
deliver in Chinese as long as an English version of the material is
available.
IBIS SUMMIT
This meeting will be conducted as a formal IBIS Summit Meeting.
Presentations will be archived in an electronic format on our
Summits site, and minutes of the meeting will be issued. However,
no formal decisions requiring votes will be planned.
CALL FOR PARTICIPANTS
People involved in IBIS and interconnect model development, EDA
tool development, and digital circuit design are invited to
participate in the Summit meeting. If you plan to participate,
please register using the information below (in English):
Name:
E-mail address:
Company:
Top-level Web Link:
Country:
Telephone:
Comments:
Send to BOTH:
Bob Ross, Teraspeed Consulting Group bob@teraspeed.com
Polin Chi, Sigrity polinchi@sigrity.com
SIGNUP DEADLINE: November 15, 2011
AGENDA
8:00 - 9:00 Vendor table setup and tables
8:00 - 9:00 Sign in
9:00 - 12:00 Presentations
12:00 - 13:30 Free buffet lunch, vendor tables
13:30 - 16:30 Presentations
Planned Presentations:
IBIS Status and Future Directions
(Intel Corporation)
IBIS Parsers
(Teraspeed Consulting Group)
Power Aware Features of IBISv5.0 - Accuracy and Challenges
(STMicroelectronics)
Modeling the On-die De-cap of IBIS 5.0 PDN-aware Buffers
(IO Methodology and Micron Technology)
Power-aware I/O Modeling for High-speed Parallel Bus Simulation
(Sigrity)
Board-Only Power Delivery Prediction for Voltage Regulator
and Mother Board Designs
(Intel Corporation)
Supporting External Circuit as Spice or S-parameters in
Conjunction with I-V/V-T Tables
(IBM and Cadence Design Systems)
T-Coils and Bridged-T Networks
(Teraspeed Consulting Group)
LIST OF NEARBY HOTELS AND TRAVEL RULES
Hotels in all price ranges can be found through internet searches.
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